linux-kernel - Re: [PATCH 1/2] platform/chrome: cros_ec

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Mon, 18 Jul 2022 11:37:31 +0300
From:   Heikki Krogerus <heikki.krogerus@...ux.intel.com>
To:     Prashant Malani <pmalani@...omium.org>
Cc:     linux-kernel@...r.kernel.org, chrome-platform@...ts.linux.dev,
        bleung@...omium.org, Guenter Roeck <groeck@...omium.org>
Subject: Re: [PATCH 1/2] platform/chrome: cros_ec_typec: Rename port altmode
 array

On Tue, Jul 12, 2022 at 09:03:17PM +0000, Prashant Malani wrote:
> Rename "p_altmode" to "port_altmode" which is a less ambiguous name for
> the port_altmode struct array.
> 
> Signed-off-by: Prashant Malani <pmalani@...omium.org>

Acked-by: Heikki Krogerus <heikki.krogerus@...ux.intel.com>

> ---
>  drivers/platform/chrome/cros_ec_typec.c | 15 +++++++--------
>  1 file changed, 7 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/platform/chrome/cros_ec_typec.c b/drivers/platform/chrome/cros_ec_typec.c
> index d6088ba447af..b9848e80f372 100644
> --- a/drivers/platform/chrome/cros_ec_typec.c
> +++ b/drivers/platform/chrome/cros_ec_typec.c
> @@ -60,8 +60,7 @@ struct cros_typec_port {
>  	uint8_t mux_flags;
>  	uint8_t role;
>  
> -	/* Port alt modes. */
> -	struct typec_altmode p_altmode[CROS_EC_ALTMODE_MAX];
> +	struct typec_altmode port_altmode[CROS_EC_ALTMODE_MAX];
>  
>  	/* Flag indicating that PD partner discovery data parsing is completed. */
>  	bool sop_disc_done;
> @@ -282,16 +281,16 @@ static void cros_typec_register_port_altmodes(struct cros_typec_data *typec,
>  	struct cros_typec_port *port = typec->ports[port_num];
>  
>  	/* All PD capable CrOS devices are assumed to support DP altmode. */
> -	port->p_altmode[CROS_EC_ALTMODE_DP].svid = USB_TYPEC_DP_SID;
> -	port->p_altmode[CROS_EC_ALTMODE_DP].mode = USB_TYPEC_DP_MODE;
> +	port->port_altmode[CROS_EC_ALTMODE_DP].svid = USB_TYPEC_DP_SID;
> +	port->port_altmode[CROS_EC_ALTMODE_DP].mode = USB_TYPEC_DP_MODE;
>  
>  	/*
>  	 * Register TBT compatibility alt mode. The EC will not enter the mode
>  	 * if it doesn't support it, so it's safe to register it unconditionally
>  	 * here for now.
>  	 */
> -	port->p_altmode[CROS_EC_ALTMODE_TBT].svid = USB_TYPEC_TBT_SID;
> -	port->p_altmode[CROS_EC_ALTMODE_TBT].mode = TYPEC_ANY_MODE;
> +	port->port_altmode[CROS_EC_ALTMODE_TBT].svid = USB_TYPEC_TBT_SID;
> +	port->port_altmode[CROS_EC_ALTMODE_TBT].mode = TYPEC_ANY_MODE;
>  
>  	port->state.alt = NULL;
>  	port->state.mode = TYPEC_STATE_USB;
> @@ -431,7 +430,7 @@ static int cros_typec_enable_tbt(struct cros_typec_data *typec,
>  		data.enter_vdo |= TBT_ENTER_MODE_ACTIVE_CABLE;
>  
>  	if (!port->state.alt) {
> -		port->state.alt = &port->p_altmode[CROS_EC_ALTMODE_TBT];
> +		port->state.alt = &port->port_altmode[CROS_EC_ALTMODE_TBT];
>  		ret = cros_typec_usb_safe_state(port);
>  		if (ret)
>  			return ret;
> @@ -473,7 +472,7 @@ static int cros_typec_enable_dp(struct cros_typec_data *typec,
>  	/* Configuration VDO. */
>  	dp_data.conf = DP_CONF_SET_PIN_ASSIGN(pd_ctrl->dp_mode);
>  	if (!port->state.alt) {
> -		port->state.alt = &port->p_altmode[CROS_EC_ALTMODE_DP];
> +		port->state.alt = &port->port_altmode[CROS_EC_ALTMODE_DP];
>  		ret = cros_typec_usb_safe_state(port);
>  		if (ret)
>  			return ret;
> -- 
> 2.37.0.144.g8ac04bfd2-goog

-- 
heikki