[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <CAMuHMdUBZ791fxCPkKQ6HCwLE4GJB2S35QC=SQ+X8w5Q4C_70g@mail.gmail.com>
Date: Tue, 19 Jul 2022 16:22:09 +0200
From: Geert Uytterhoeven <geert@...ux-m68k.org>
To: Sudeep Holla <sudeep.holla@....com>
Cc: Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Conor Dooley <conor.dooley@...rochip.com>,
valentina.fernandezalanis@...rochip.com,
Vincent Guittot <vincent.guittot@...aro.org>,
Dietmar Eggemann <dietmar.eggemann@....com>,
Qing Wang <wangqing@...o.com>,
Rob Herring <robh+dt@...nel.org>,
"Rafael J . Wysocki" <rafael@...nel.org>,
Ionela Voinescu <ionela.voinescu@....com>,
Pierre Gondois <pierre.gondois@....com>,
Linux ARM <linux-arm-kernel@...ts.infradead.org>,
linux-riscv <linux-riscv@...ts.infradead.org>,
Gavin Shan <gshan@...hat.com>
Subject: Re: [PATCH v6 09/21] arch_topology: Add support to parse and detect
cache attributes
Hi Sudeep,
On Mon, Jul 4, 2022 at 12:19 PM Sudeep Holla <sudeep.holla@....com> wrote:
> Currently ACPI populates just the minimum information about the last
> level cache from PPTT in order to feed the same to build sched_domains.
> Similar support for DT platforms is not present.
>
> In order to enable the same, the entire cache hierarchy information can
> be built as part of CPU topoplogy parsing both on ACPI and DT platforms.
>
> Note that this change builds the cacheinfo early even on ACPI systems,
> but the current mechanism of building llc_sibling mask remains unchanged.
>
> Tested-by: Ionela Voinescu <ionela.voinescu@....com>
> Reviewed-by: Gavin Shan <gshan@...hat.com>
> Signed-off-by: Sudeep Holla <sudeep.holla@....com>
Thanks for your patch!
> --- a/drivers/base/arch_topology.c
> +++ b/drivers/base/arch_topology.c
> @@ -7,6 +7,7 @@
> */
>
> #include <linux/acpi.h>
> +#include <linux/cacheinfo.h>
> #include <linux/cpu.h>
> #include <linux/cpufreq.h>
> #include <linux/device.h>
> @@ -780,15 +781,28 @@ __weak int __init parse_acpi_topology(void)
> #if defined(CONFIG_ARM64) || defined(CONFIG_RISCV)
> void __init init_cpu_topology(void)
> {
> + int ret, cpu;
> +
> reset_cpu_topology();
> + ret = parse_acpi_topology();
> + if (!ret)
> + ret = of_have_populated_dt() && parse_dt_topology();
>
> - /*
> - * Discard anything that was parsed if we hit an error so we
> - * don't use partial information.
> - */
> - if (parse_acpi_topology())
> - reset_cpu_topology();
> - else if (of_have_populated_dt() && parse_dt_topology())
> + if (ret) {
> + /*
> + * Discard anything that was parsed if we hit an error so we
> + * don't use partial information.
> + */
> reset_cpu_topology();
> + return;
> + }
> +
> + for_each_possible_cpu(cpu) {
> + ret = detect_cache_attributes(cpu);
> + if (ret) {
> + pr_info("Early cacheinfo failed, ret = %d\n", ret);
This is triggered
Early cacheinfo failed, ret = -12
on all my RV64 platforms (K210, PolarFire, StarLight).
-12 = -ENOMEM.
The boot continues regardless, and the K210 even has enough spare
RAM after boot to run "ls", unlike two weeks ago ;-)
> + break;
> + }
> + }
> }
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Powered by blists - more mailing lists