linux-kernel - Re: [PATCH] regmap: support regmap_field

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Message-ID: <53242a5b-0ba0-71c6-3b6c-e3a628b7eda1@linaro.org>
Date:   Tue, 19 Jul 2022 18:00:53 +0200
From:   Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To:     Mark Brown <broonie@...nel.org>
Cc:     Charles Keepax <ckeepax@...nsource.cirrus.com>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        "Rafael J. Wysocki" <rafael@...nel.org>,
        linux-kernel@...r.kernel.org,
        Srinivas Kandagatla <srinivas.kandagatla@...aro.org>,
        Kuninori Morimoto <kuninori.morimoto.gx@...esas.com>,
        Bjorn Andersson <bjorn.andersson@...aro.org>
Subject: Re: [PATCH] regmap: support regmap_field_write() on non-readable
 fields

On 19/07/2022 16:30, Krzysztof Kozlowski wrote:
> On 19/07/2022 15:41, Mark Brown wrote:
>> On Tue, Jul 19, 2022 at 03:13:11PM +0200, Krzysztof Kozlowski wrote:
>>> On 19/07/2022 14:54, Charles Keepax wrote:
>>
>>>> I think this will break other valid use-cases, regmap_readable (I
>>>> believe) returns if the register is physically readable, however
>>>> it should still be possible to use update bits if the register is
>>>> in the cache even if it can't physically be read. So really you
>>>> need to fall into this path if it is readable or in the cache.
>>
>>> But what type of real use case this would be trying to solve? Either
>>> register is readable or not. The presence of cache is just optimization
>>> and does not change the fact that we cannot read from register thus no
>>> need to go via updates.
>>
>> The original reason for creating the cache code was to simulate
>> readability on devices that have no read support at all (think 7x9
>> format I2C devices) so we can have things like helpers to map bitfields
>> directly to subsystems (like ASoC uses extensively).  The fact that it
>> also improves performance when the hardware does support reads is nice
>> too of course.
>>
>>>> Which does I guess also raise the question if your problem would
>>>> be better solved with caching the register?
>>
>>> And how the value would appear in the cache? Since register cannot be
>>> read, I expect the cache to be filled on first update. First update
>>> would be read+write, so we are stuck again.
>>
>> This is one reason we allow cache defaults to be specified (it was the
>> original reason, we later started using them to optimise out I/O during
>> resyncs).
> 
> Thanks Mark and Charles. Let me try the cache.

cache + forced write works for me, so I guess this patch is not really
necessary.

Best regards,
Krzysztof