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Message-Id: <165825301043.2954553.8589641722040434945.b4-ty@kernel.org>
Date: Tue, 19 Jul 2022 20:56:49 +0100
From: Will Deacon <will@...nel.org>
To: Anshuman Khandual <anshuman.khandual@....com>,
linux-arm-kernel@...ts.infradead.org
Cc: catalin.marinas@....com, kernel-team@...roid.com,
Will Deacon <will@...nel.org>,
Alexey Budankov <alexey.budankov@...ux.intel.com>,
suzuki.poulose@....com, Mark Rutland <mark.rutland@....com>,
german.gomez@....com, linux-kernel@...r.kernel.org,
james.clark@....com
Subject: Re: [PATCH v3] drivers/perf: arm_spe: Fix consistency of SYS_PMSCR_EL1.CX
On Thu, 14 Jul 2022 11:43:02 +0530, Anshuman Khandual wrote:
> The arm_spe_pmu driver will enable SYS_PMSCR_EL1.CX in order to add CONTEXT
> packets into the traces, if the owner of the perf event runs with required
> capabilities i.e CAP_PERFMON or CAP_SYS_ADMIN via perfmon_capable() helper.
>
> The value of this bit is computed in the arm_spe_event_to_pmscr() function
> but the check for capabilities happens in the pmu event init callback i.e
> arm_spe_pmu_event_init(). This suggests that the value of the CX bit should
> remain consistent for the duration of the perf session.
>
> [...]
Applied to will (for-next/perf), thanks!
[1/1] drivers/perf: arm_spe: Fix consistency of SYS_PMSCR_EL1.CX
https://git.kernel.org/will/c/92f2b8bafa3d
Cheers,
--
Will
https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev
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