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Message-ID: <0e038c2795784b7eb4de52f77b67206a@AcuMS.aculab.com>
Date: Tue, 19 Jul 2022 08:26:35 +0000
From: David Laight <David.Laight@...LAB.COM>
To: 'Linus Torvalds' <torvalds@...ux-foundation.org>,
Thomas Gleixner <tglx@...utronix.de>
CC: Sami Tolvanen <samitolvanen@...gle.com>,
Joao Moreira <joao@...rdrivepizza.com>,
Peter Zijlstra <peterz@...radead.org>,
LKML <linux-kernel@...r.kernel.org>,
the arch/x86 maintainers <x86@...nel.org>,
Tim Chen <tim.c.chen@...ux.intel.com>,
Josh Poimboeuf <jpoimboe@...nel.org>,
"Cooper, Andrew" <andrew.cooper3@...rix.com>,
Pawan Gupta <pawan.kumar.gupta@...ux.intel.com>,
Johannes Wikner <kwikner@...z.ch>,
Alyssa Milburn <alyssa.milburn@...ux.intel.com>,
Jann Horn <jannh@...gle.com>, "H.J. Lu" <hjl.tools@...il.com>,
"Moreira, Joao" <joao.moreira@...el.com>,
"Nuzman, Joseph" <joseph.nuzman@...el.com>,
"Steven Rostedt" <rostedt@...dmis.org>,
"Gross, Jurgen" <jgross@...e.com>,
"Masami Hiramatsu" <mhiramat@...nel.org>,
Alexei Starovoitov <ast@...nel.org>,
"Daniel Borkmann" <daniel@...earbox.net>,
Peter Collingbourne <pcc@...gle.com>
Subject: RE: [patch 00/38] x86/retbleed: Call depth tracking mitigation
From: Linus Torvalds
> Sent: 19 July 2022 01:02
>
> On Mon, Jul 18, 2022 at 4:52 PM Linus Torvalds
> <torvalds@...ux-foundation.org> wrote:
> >
> > Honestly, I think that would be a better model - yes, you lose 8 bits
> > of hash, but considering that apparently the current KCFI code
> > *guarantees* that the hash pattern will exist even outside the actual
> > target pattern,
>
> Gaah, I'm being stupid,. You still get the value collision, since the
> int3 byte pattern would just be part of the compare pattern.
>
> You'd have to use some multi-instruction compare to avoid having the
> pattern in the instruction stream. Probably with another register.
> Like
>
> movl -FIXED_OFFSET(%eax),%rdx
> addl $ANTI_PATTERN,%rdx
> je ok
>
> so that the "compare" wouldn't use the same pattern value, but be an
> add with the negated pattern value instead.
>
> The extra instruction is likely less of a problem than the extra register used.
Shouldn't it be testing the value the caller supplied?
The extra instruction is likely to be one clock - I doubt it will
sensibly run in parallel with code later in the function.
The larger costs are (probably) polluting the D$ with I addresses
(already done by the caller) and the likely mispredicted 'je ok'.
Unless the function has been recently called the 'je ok' gets
static prediction.
While traditionally that would predict a forwards branch 'not taken'
ISTR more recent Intel cpu just use the predictor output - ie random.
Not at all sure about AMD cpu though.
David
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