linux-kernel - RE: [RFC 2/2] PCI: imx6: Support more than Gen2 speed link mode

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Message-ID: <AS8PR04MB8676EF521BAD0F98AE6CA9DD8C8E9@AS8PR04MB8676.eurprd04.prod.outlook.com>
Date:   Wed, 20 Jul 2022 01:43:55 +0000
From:   Hongxing Zhu <hongxing.zhu@....com>
To:     "tharvey@...eworks.com" <tharvey@...eworks.com>
CC:     Lucas Stach <l.stach@...gutronix.de>,
        "bhelgaas@...gle.com" <bhelgaas@...gle.com>,
        Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
        Fabio Estevam <festevam@...il.com>,
        "linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
        Linux ARM Mailing List <linux-arm-kernel@...ts.infradead.org>,
        open list <linux-kernel@...r.kernel.org>,
        Sascha Hauer <kernel@...gutronix.de>,
        dl-linux-imx <linux-imx@....com>
Subject: RE: [RFC 2/2] PCI: imx6: Support more than Gen2 speed link mode

> -----Original Message-----
> From: Tim Harvey <tharvey@...eworks.com>
> Sent: 2022年7月20日 8:59
> To: Hongxing Zhu <hongxing.zhu@....com>
> Cc: Lucas Stach <l.stach@...gutronix.de>; bhelgaas@...gle.com; Lorenzo
> Pieralisi <lorenzo.pieralisi@....com>; Fabio Estevam <festevam@...il.com>;
> linux-pci@...r.kernel.org; Linux ARM Mailing List
> <linux-arm-kernel@...ts.infradead.org>; open list
> <linux-kernel@...r.kernel.org>; Sascha Hauer <kernel@...gutronix.de>;
> dl-linux-imx <linux-imx@....com>
> Subject: Re: [RFC 2/2] PCI: imx6: Support more than Gen2 speed link mode
> 
> On Wed, May 18, 2022 at 2:49 AM Richard Zhu <hongxing.zhu@....com>
> wrote:
> >
> > Support more than Gen2 speed link mode, since i.MX8MP PCIe supports up
> > to Gen3 link speed.
> >
> > Signed-off-by: Richard Zhu <hongxing.zhu@....com>
> > ---
> >  drivers/pci/controller/dwc/pci-imx6.c | 4 ++--
> >  1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/pci/controller/dwc/pci-imx6.c
> > b/drivers/pci/controller/dwc/pci-imx6.c
> > index 30641d2dda14..37012f9a33a0 100644
> > --- a/drivers/pci/controller/dwc/pci-imx6.c
> > +++ b/drivers/pci/controller/dwc/pci-imx6.c
> > @@ -809,8 +809,8 @@ static int imx6_pcie_start_link(struct dw_pcie
> > *pci)
> >
> >         dw_pcie_wait_for_link(pci);
> >
> > -       if (pci->link_gen == 2) {
> > -               /* Allow Gen2 mode after the link is up. */
> > +       if (pci->link_gen > 1) {
> > +               /* Allow faster modes after the link is up. */
> >                 dw_pcie_dbi_ro_wr_en(pci);
> >                 tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
> >                 tmp &= ~PCI_EXP_LNKCAP_SLS;
> > --
> 
> Richard,
> 
> I noticed that your imx8mp pcie series [1] will force the imx8mp to link only at
> gen1 speeds unless support like the above is added. I believe you would also
> need the following:
> -               tmp |= PCI_EXP_LNKCAP_SLS_5_0GB;
> +               tmp |= pci->link_gen;
> 
> When I used this along with your imx8mp series however I only get a gen1 link.
> 
> Have you made any progress on a v3 of your imx8mp series?
> 
> Do you know if the downstream NXP vendor kernel [2] supports imx8mp Gen3
> links?
Hi Tim:
Thanks for your timely reminder. I just was puzzled a while why only Gen1 is
 linked up on i.MX8MP.
Root cause is that I forget merge some local changes to the up-stream codes.
BTW, the local codes supports the Gen3 link on i.MX8MP A1 chip or later.
Since the A0 chip PCIe only supports up to Gen2 link speed.

Best Regards
Richard Zhu

> 
> Best Regards,
> 
> Tim
> [1]
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchw
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