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Date: Wed, 20 Jul 2022 14:51:08 +0900
From: Wangseok Lee <wangseok.lee@...sung.com>
To: "robh+dt@...nel.org" <robh+dt@...nel.org>,
"krzk+dt@...nel.org" <krzk+dt@...nel.org>,
"kishon@...com" <kishon@...com>,
"vkoul@...nel.org" <vkoul@...nel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"jesper.nilsson@...s.com" <jesper.nilsson@...s.com>,
"lars.persson@...s.com" <lars.persson@...s.com>,
"bhelgaas@...gle.com" <bhelgaas@...gle.com>,
"linux-phy@...ts.infradead.org" <linux-phy@...ts.infradead.org>,
"linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"lorenzo.pieralisi@....com" <lorenzo.pieralisi@....com>,
"kw@...ux.com" <kw@...ux.com>,
"linux-arm-kernel@...s.com" <linux-arm-kernel@...s.com>,
"kernel@...s.com" <kernel@...s.com>
CC: Moon-Ki Jun <moonki.jun@...sung.com>,
Sang Min Kim <hypmean.kim@...sung.com>,
Dongjin Yang <dj76.yang@...sung.com>,
Yeeun Kim <yeeun119.kim@...sung.com>,
Wangseok Lee <wangseok.lee@...sung.com>
Subject: [PATCH v4 0/5] Add support for Axis, ARTPEC-8 PCIe driver
This v4 patchset is improvement several review comments received from patchset v3.
Main changes since v3 [3]:
dt-bindings: pci: Add ARTPEC-8 PCIe controller
-add missing properties
dt-bindings: phy: Add ARTPEC-8 PCIe phy
-add "fsys-sysreg" to properties
-modify the "lcpll-ref-clk" and "clocks" in properties
"lcpll-ref-clk" is custom properties, so add 'vendor', type(enum),
description
Add the maxItem in clocks, add clock-names in properties
PCI: axis: Add ARTPEC-8 PCIe controller driver
-remove unnecessary enum type
-fix indentation
phy: Add ARTPEC-8 PCIe PHY driver
-modify to use GENMASK
-fix indentation
-remove the driver data
Main changes since v2 [2]:
dt-bindings: pci: Add ARTPEC-8 PCIe controller
-modify version history to fit the linux commit rule
-remove 'Device Tree Bindings' on title
-remove the interrupt-names, phy-names entries
-remove '_clk' suffix
-add the compatible entries on required
-change node name to soc from artpec8 on examples
dt-bindings: phy: Add ARTPEC-8 PCIe phy
-modify version history to fit the linux commit rule
-remove 'Device Tree Bindings' on title
-remove clock-names entries
-change node name to soc from artpec8 on excamples
PCI: axis: Add ARTPEC-8 PCIe controller driver
-add 'COMPILE_TEST' and improvement help on kconfig
-reorder obj on makefile
-use clk_bulk_api
-remove unnecessary comment
-redefine the ELBI register to distinguish between offset and
bit definition
-improvement order local variable of function
-remove unnecessary local return variable
phy: Add ARTPEC-8 PCIe PHY driver
-remove unnecessary indentation
-redefine local struct to statis const
-add static const to struct that requires static const definition
-remove wrappers on writel and readl
Main changes since v1 [1]:
-'make dt_binding_check' result improvement
-Add the missing property list
-improvement review comment of Krzysztof on driver code
-change folder name of phy driver to axis from artpec
[3] https://lore.kernel.org/lkml/20220614011616epcms2p7dcaa67c53b7df5802dd7a697e2d472d7@epcms2p7/T
[2] https://lore.kernel.org/lkml/20220613015023epcms2p70e6700a99042d4deb560e40ab5397001@epcms2p7/T/
[1] https://lore.kernel.org/lkml/20220328014430epcms2p7063834feb0abdf2f38a62723c96c9ff1@epcms2p7/
--------------------------------------------------------------
This series patches include newly PCIe support for Axis ARTPEC-8 SoC.
ARTPEC-8 is the SoC platform of Axis Communications.
PCIe controller driver and phy driver have been newly added.
There is also a new MAINTAINER in the addition of phy driver.
PCIe controller is designed based on Design-Ware PCIe controller IP
and PCIe phy is desinged based on SAMSUNG PHY IP.
It also includes modifications to the Design-Ware controller driver to
run the 64bit-based ARTPEC-8 PCIe controller driver.
It consists of 6 patches in total.
This series has been tested on AXIS SW bring-up board
with ARTPEC-8 chipset.
--------------------------------------------------------------
Wangseok Lee (5):
dt-bindings: pci: Add ARTPEC-8 PCIe controller
dt-bindings: phy: Add ARTPEC-8 PCIe phy
PCI: axis: Add ARTPEC-8 PCIe controller driver
phy: Add ARTPEC-8 PCIe PHY driver
MAINTAINERS: Add Axis ARTPEC-8 PCIe PHY maintainers
.../bindings/pci/axis,artpec8-pcie-ep.yaml | 138 ++++
.../devicetree/bindings/pci/axis,artpec8-pcie.yaml | 148 ++++
.../bindings/phy/axis,artpec8-pcie-phy.yaml | 85 +++
MAINTAINERS | 2 +
drivers/pci/controller/dwc/Kconfig | 31 +
drivers/pci/controller/dwc/Makefile | 1 +
drivers/pci/controller/dwc/pcie-artpec8.c | 788 +++++++++++++++++++++
drivers/phy/Kconfig | 1 +
drivers/phy/Makefile | 1 +
drivers/phy/axis/Kconfig | 9 +
drivers/phy/axis/Makefile | 2 +
drivers/phy/axis/phy-artpec8-pcie.c | 753 ++++++++++++++++++++
12 files changed, 1959 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/axis,artpec8-pcie-ep.yaml
create mode 100644 Documentation/devicetree/bindings/pci/axis,artpec8-pcie.yaml
create mode 100644 Documentation/devicetree/bindings/phy/axis,artpec8-pcie-phy.yaml
create mode 100644 drivers/pci/controller/dwc/pcie-artpec8.c
create mode 100644 drivers/phy/axis/Kconfig
create mode 100644 drivers/phy/axis/Makefile
create mode 100644 drivers/phy/axis/phy-artpec8-pcie.c
--
2.9.5
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