[<prev] [next>] [thread-next>] [day] [month] [year] [list]
Message-Id: <20220720112748.17752-1-slark_xiao@163.com>
Date: Wed, 20 Jul 2022 19:27:48 +0800
From: Slark Xiao <slark_xiao@....com>
To: robh+dt@...nel.org, krzysztof.kozlowski+dt@...aro.org
Cc: devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
Slark Xiao <slark_xiao@....com>
Subject: [PATCH] dt-bindings: arm: msm: Fix typo in comment
Fix typo in the comment
Signed-off-by: Slark Xiao <slark_xiao@....com>
---
Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt b/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt
index 94d50a949be1..c0e3c3a42bea 100644
--- a/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt
@@ -10,7 +10,7 @@ system, notifying them when a low power state is entered or exited.
Multiple revisions of the SAW hardware are supported using these Device Nodes.
SAW2 revisions differ in the register offset and configuration data. Also, the
same revision of the SAW in different SoCs may have different configuration
-data due the the differences in hardware capabilities. Hence the SoC name, the
+data due the differences in hardware capabilities. Hence the SoC name, the
version of the SAW hardware in that SoC and the distinction between cpu (big
or Little) or cache, may be needed to uniquely identify the SAW register
configuration and initialization data. The compatible string is used to
--
2.25.1
Powered by blists - more mailing lists