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Date: Thu, 21 Jul 2022 14:20:42 +0000
From: Camelia Alexandra Groza <camelia.groza@....com>
To: Sean Anderson <sean.anderson@...o.com>,
"David S . Miller" <davem@...emloft.net>,
Jakub Kicinski <kuba@...nel.org>,
Madalin Bucur <madalin.bucur@....com>,
"netdev@...r.kernel.org" <netdev@...r.kernel.org>
CC: Paolo Abeni <pabeni@...hat.com>,
Eric Dumazet <edumazet@...gle.com>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
Russell King <linux@...linux.org.uk>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
Sean Anderson <sean.anderson@...o.com>,
Kishon Vijay Abraham I <kishon@...com>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Leo Li <leoyang.li@....com>, Rob Herring <robh+dt@...nel.org>,
Shawn Guo <shawnguo@...nel.org>, Vinod Koul <vkoul@...nel.org>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"linux-phy@...ts.infradead.org" <linux-phy@...ts.infradead.org>
Subject: RE: [PATCH net-next v3 46/47] arm64: dts: ls1046ardb: Add serdes
bindings
> -----Original Message-----
> From: Sean Anderson <sean.anderson@...o.com>
> Sent: Saturday, July 16, 2022 1:00
> To: David S . Miller <davem@...emloft.net>; Jakub Kicinski
> <kuba@...nel.org>; Madalin Bucur <madalin.bucur@....com>;
> netdev@...r.kernel.org
> Cc: Paolo Abeni <pabeni@...hat.com>; Eric Dumazet
> <edumazet@...gle.com>; linux-arm-kernel@...ts.infradead.org; Russell
> King <linux@...linux.org.uk>; linux-kernel@...r.kernel.org; Sean Anderson
> <sean.anderson@...o.com>; Kishon Vijay Abraham I <kishon@...com>;
> Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>; Leo Li
> <leoyang.li@....com>; Rob Herring <robh+dt@...nel.org>; Shawn Guo
> <shawnguo@...nel.org>; Vinod Koul <vkoul@...nel.org>;
> devicetree@...r.kernel.org; linux-phy@...ts.infradead.org
> Subject: [PATCH net-next v3 46/47] arm64: dts: ls1046ardb: Add serdes
> bindings
>
> This adds appropriate bindings for the macs which use the SerDes. The
> 156.25MHz fixed clock is a crystal. The 100MHz clocks (there are
> actually 3) come from a Renesas 6V49205B at address 69 on i2c0. There is
> no driver for this device (and as far as I know all you can do with the
> 100MHz clocks is gate them), so I have chosen to model it as a single
> fixed clock.
>
> Note: the SerDes1 lane numbering for the LS1046A is *reversed*.
> This means that Lane A (what the driver thinks is lane 0) uses pins
> SD1_TX3_P/N.
>
> Because this will break ethernet if the serdes is not enabled, enable
> the serdes driver by default on Layerscape.
>
> Signed-off-by: Sean Anderson <sean.anderson@...o.com>
> ---
> Please let me know if there is a better/more specific config I can use
> here.
>
> (no changes since v1)
My LS1046ARDB hangs at boot with this patch right after the second SerDes is probed,
right before the point where the PCI host bridge is registered. I can get around this
either by disabling the second SerDes node from the device tree, or disabling
CONFIG_PCI_LAYERSCAPE at build.
I haven't debugged it more but there seems to be an issue here.
> .../boot/dts/freescale/fsl-ls1046a-rdb.dts | 34 +++++++++++++++++++
> drivers/phy/freescale/Kconfig | 1 +
> 2 files changed, 35 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
> b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
> index 7025aad8ae89..4f4dd0ed8c53 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
> @@ -26,6 +26,32 @@ aliases {
> chosen {
> stdout-path = "serial0:115200n8";
> };
> +
> + clocks {
> + clk_100mhz: clock-100mhz {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <100000000>;
> + };
> +
> + clk_156mhz: clock-156mhz {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <156250000>;
> + };
> + };
> +};
> +
> +&serdes1 {
> + clocks = <&clk_100mhz>, <&clk_156mhz>;
> + clock-names = "ref0", "ref1";
> + status = "okay";
> +};
> +
> +&serdes2 {
> + clocks = <&clk_100mhz>, <&clk_100mhz>;
> + clock-names = "ref0", "ref1";
> + status = "okay";
> };
>
> &duart0 {
> @@ -140,21 +166,29 @@ ethernet@...00 {
> ethernet@...00 {
> phy-handle = <&sgmii_phy1>;
> phy-connection-type = "sgmii";
> + phys = <&serdes1 1>;
> + phy-names = "serdes";
> };
>
> ethernet@...00 {
> phy-handle = <&sgmii_phy2>;
> phy-connection-type = "sgmii";
> + phys = <&serdes1 0>;
> + phy-names = "serdes";
> };
>
> ethernet@...00 { /* 10GEC1 */
> phy-handle = <&aqr106_phy>;
> phy-connection-type = "xgmii";
> + phys = <&serdes1 3>;
> + phy-names = "serdes";
> };
>
> ethernet@...00 { /* 10GEC2 */
> fixed-link = <0 1 1000 0 0>;
> phy-connection-type = "xgmii";
> + phys = <&serdes1 2>;
> + phy-names = "serdes";
> };
>
> mdio@...00 {
> diff --git a/drivers/phy/freescale/Kconfig b/drivers/phy/freescale/Kconfig
> index fe2a3efe0ba4..9595666213d0 100644
> --- a/drivers/phy/freescale/Kconfig
> +++ b/drivers/phy/freescale/Kconfig
> @@ -43,6 +43,7 @@ config PHY_FSL_LYNX_10G
> tristate "Freescale Layerscale Lynx 10G SerDes support"
> select GENERIC_PHY
> select REGMAP_MMIO
> + default y if ARCH_LAYERSCAPE
> help
> This adds support for the Lynx "SerDes" devices found on various
> QorIQ
> SoCs. There may be up to four SerDes devices on each SoC, and
> each
> --
> 2.35.1.1320.gc452695387.dirty
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