linux-kernel - Re: [PATCH v5 11/15] KVM: nVMX: Set UMIP bit CR4

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Message-ID: <40500f56-5ea4-f0c3-2a75-290ed20c9c81@redhat.com>
Date:   Fri, 22 Jul 2022 11:49:25 +0200
From:   Paolo Bonzini <pbonzini@...hat.com>
To:     Sean Christopherson <seanjc@...gle.com>
Cc:     Vitaly Kuznetsov <vkuznets@...hat.com>,
        Wanpeng Li <wanpengli@...cent.com>,
        Jim Mattson <jmattson@...gle.com>,
        Joerg Roedel <joro@...tes.org>, kvm@...r.kernel.org,
        linux-kernel@...r.kernel.org, Eric Li <ercli@...avis.edu>,
        David Matlack <dmatlack@...gle.com>,
        Oliver Upton <oupton@...gle.com>
Subject: Re: [PATCH v5 11/15] KVM: nVMX: Set UMIP bit CR4_FIXED1 MSR when
 emulating UMIP

On 6/7/22 23:36, Sean Christopherson wrote:
> Make UMIP an "allowed-1" bit CR4_FIXED1 MSR when KVM is emulating UMIP.
> KVM emulates UMIP for both L1 and L2, and so should enumerate that L2 is
> allowed to have CR4.UMIP=1.  Not setting the bit doesn't immediately
> break nVMX, as KVM does set/clear the bit in CR4_FIXED1 in response to a
> guest CPUID update, i.e. KVM will correctly (dis)allow nested VM-Entry
> based on whether or not UMIP is exposed to L1.
> 
> That said, KVM should enumerate the bit as being allowed from time zero,
> e.g. userspace will see the wrong value if the MSR is read before CPUID
> is written.  And a future patch will quirk KVM's behavior of stuffing
> CR4_FIXED1 in response to guest CPUID changes, as CR4_FIXED1 is not
> strictly required to match the CPUID model exposed to L1.

I'm not sure about this; there's no *practical* need to allow it, since 
there is generally a 1:n mapping between CPUID and CR4 reserved bits. 
Do you mind removing the "future patch" reference from the commit message?

Paolo