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Message-ID: <BY5PR12MB4033037009559D6A0BE5571193909@BY5PR12MB4033.namprd12.prod.outlook.com>
Date: Fri, 22 Jul 2022 15:23:36 +0000
From: "Neeli, Srinivas" <srinivas.neeli@....com>
To: Srinivas Neeli <srinivas.neeli@...inx.com>,
"a.zummo@...ertech.it" <a.zummo@...ertech.it>,
"alexandre.belloni@...tlin.com" <alexandre.belloni@...tlin.com>,
"robh+dt@...nel.org" <robh+dt@...nel.org>,
"neelisrinivas18@...il.com" <neelisrinivas18@...il.com>,
"krzysztof.kozlowski+dt@...aro.org"
<krzysztof.kozlowski+dt@...aro.org>,
"michal.simek@...inx.com" <michal.simek@...inx.com>,
"sgoud@...inx.com" <sgoud@...inx.com>,
"shubhraj@...inx.com" <shubhraj@...inx.com>
CC: "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"linux-rtc@...r.kernel.org" <linux-rtc@...r.kernel.org>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"git (AMD-Xilinx)" <git@....com>, "git@...inx.com" <git@...inx.com>
Subject: RE: [PATCH V10 3/3] rtc: zynqmp: Add calibration set and get support
Hi,
Is there any comments on this patch ?.
Thanks
Neeli Srinivas
> -----Original Message-----
> From: Srinivas Neeli <srinivas.neeli@...inx.com>
> Sent: Sunday, June 26, 2022 12:38 PM
> To: a.zummo@...ertech.it; alexandre.belloni@...tlin.com;
> robh+dt@...nel.org; Neeli, Srinivas <srinivas.neeli@....com>;
> neelisrinivas18@...il.com; krzysztof.kozlowski+dt@...aro.org;
> michal.simek@...inx.com; sgoud@...inx.com; shubhraj@...inx.com
> Cc: devicetree@...r.kernel.org; linux-rtc@...r.kernel.org; linux-arm-
> kernel@...ts.infradead.org; linux-kernel@...r.kernel.org; git (AMD-Xilinx)
> <git@....com>; git@...inx.com; Srinivas Neeli <srinivas.neeli@...inx.com>
> Subject: [PATCH V10 3/3] rtc: zynqmp: Add calibration set and get support
>
> Zynqmp RTC controller has a calibration feature to compensate time
> deviation due to input clock inaccuracy.
> Set and get calibration API's are used for setting and getting calibration value
> from the controller calibration register.
>
> Signed-off-by: Srinivas Neeli <srinivas.neeli@...inx.com>
> ---
> Chanes in V10:
> -None
> Changes in V9:
> -None
> Changes in V8:
> -None
> Changes in V7:
> -Removed calibration default value update from this patch.
> Changes in V6:
> -None
> Changes in V5:
> -None
> Changes in V4:
> -Updated MIN and MAX calibration values.
> Changes in V3:
> -Calculated tick_mult using crystal frequency.
> -Calibration register updating based on crystal frequency in probe.
> -Supressed MIN an MAX calibration values,Will send separate patch in
> future.
> Changes in V2:
> -Removed unused macro.
> -Updated code with review comments.
> ---
> drivers/rtc/rtc-zynqmp.c | 113 ++++++++++++++++++++++++++++++++-------
> 1 file changed, 94 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/rtc/rtc-zynqmp.c b/drivers/rtc/rtc-zynqmp.c index
> 5da33d760419..1dd389b891fe 100644
> --- a/drivers/rtc/rtc-zynqmp.c
> +++ b/drivers/rtc/rtc-zynqmp.c
> @@ -6,6 +6,7 @@
> *
> */
>
> +#include <linux/clk.h>
> #include <linux/delay.h>
> #include <linux/init.h>
> #include <linux/io.h>
> @@ -40,13 +41,19 @@
> #define RTC_CALIB_MASK 0x1FFFFF
> #define RTC_ALRM_MASK BIT(1)
> #define RTC_MSEC 1000
> +#define RTC_FR_MASK 0xF0000
> +#define RTC_FR_MAX_TICKS 16
> +#define RTC_PPB 1000000000LL
> +#define RTC_MIN_OFFSET -32768000
> +#define RTC_MAX_OFFSET 32767000
>
> struct xlnx_rtc_dev {
> struct rtc_device *rtc;
> void __iomem *reg_base;
> int alarm_irq;
> int sec_irq;
> - unsigned int calibval;
> + struct clk *rtc_clk;
> + unsigned int freq;
> };
>
> static int xlnx_rtc_set_time(struct device *dev, struct rtc_time *tm) @@ -
> 61,13 +68,6 @@ static int xlnx_rtc_set_time(struct device *dev, struct
> rtc_time *tm)
> */
> new_time = rtc_tm_to_time64(tm) + 1;
>
> - /*
> - * Writing into calibration register will clear the Tick Counter and
> - * force the next second to be signaled exactly in 1 second period
> - */
> - xrtcdev->calibval &= RTC_CALIB_MASK;
> - writel(xrtcdev->calibval, (xrtcdev->reg_base + RTC_CALIB_WR));
> -
> writel(new_time, xrtcdev->reg_base + RTC_SET_TM_WR);
>
> /*
> @@ -173,15 +173,76 @@ static void xlnx_init_rtc(struct xlnx_rtc_dev
> *xrtcdev)
> rtc_ctrl = readl(xrtcdev->reg_base + RTC_CTRL);
> rtc_ctrl |= RTC_BATT_EN;
> writel(rtc_ctrl, xrtcdev->reg_base + RTC_CTRL);
> +}
>
> - /*
> - * Based on crystal freq of 33.330 KHz
> - * set the seconds counter and enable, set fractions counter
> - * to default value suggested as per design spec
> - * to correct RTC delay in frequency over period of time.
> +static int xlnx_rtc_read_offset(struct device *dev, long *offset) {
> + struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
> + unsigned long long rtc_ppb = RTC_PPB;
> + unsigned int tick_mult = do_div(rtc_ppb, xrtcdev->freq);
> + unsigned int calibval;
> + long offset_val;
> +
> + calibval = readl(xrtcdev->reg_base + RTC_CALIB_RD);
> + /* Offset with seconds ticks */
> + offset_val = calibval & RTC_TICK_MASK;
> + offset_val = offset_val - RTC_CALIB_DEF;
> + offset_val = offset_val * tick_mult;
> +
> + /* Offset with fractional ticks */
> + if (calibval & RTC_FR_EN)
> + offset_val += ((calibval & RTC_FR_MASK) >>
> RTC_FR_DATSHIFT)
> + * (tick_mult / RTC_FR_MAX_TICKS);
> + *offset = offset_val;
> +
> + return 0;
> +}
> +
> +static int xlnx_rtc_set_offset(struct device *dev, long offset) {
> + struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
> + unsigned long long rtc_ppb = RTC_PPB;
> + unsigned int tick_mult = do_div(rtc_ppb, xrtcdev->freq);
> + unsigned char fract_tick;
> + unsigned int calibval;
> + short int max_tick;
> + int fract_offset;
> +
> + if (offset < RTC_MIN_OFFSET || offset > RTC_MAX_OFFSET)
> + return -ERANGE;
> +
> + /* Number ticks for given offset */
> + max_tick = div_s64_rem(offset, tick_mult, &fract_offset);
> +
> + /* Number fractional ticks for given offset */
> + if (fract_offset) {
> + if (fract_offset < 0) {
> + fract_offset = fract_offset + tick_mult;
> + max_tick--;
> + }
> + if (fract_offset > (tick_mult / RTC_FR_MAX_TICKS)) {
> + for (fract_tick = 1; fract_tick < 16; fract_tick++) {
> + if (fract_offset <=
> + (fract_tick *
> + (tick_mult / RTC_FR_MAX_TICKS)))
> + break;
> + }
> + }
> + }
> +
> + /* Zynqmp RTC uses second and fractional tick
> + * counters for compensation
> */
> - xrtcdev->calibval &= RTC_CALIB_MASK;
> - writel(xrtcdev->calibval, (xrtcdev->reg_base + RTC_CALIB_WR));
> + calibval = max_tick + RTC_CALIB_DEF;
> +
> + if (fract_tick)
> + calibval |= RTC_FR_EN;
> +
> + calibval |= (fract_tick << RTC_FR_DATSHIFT);
> +
> + writel(calibval, (xrtcdev->reg_base + RTC_CALIB_WR));
> +
> + return 0;
> }
>
> static const struct rtc_class_ops xlnx_rtc_ops = { @@ -190,6 +251,8 @@
> static const struct rtc_class_ops xlnx_rtc_ops = {
> .read_alarm = xlnx_rtc_read_alarm,
> .set_alarm = xlnx_rtc_set_alarm,
> .alarm_irq_enable = xlnx_rtc_alarm_irq_enable,
> + .read_offset = xlnx_rtc_read_offset,
> + .set_offset = xlnx_rtc_set_offset,
> };
>
> static irqreturn_t xlnx_rtc_interrupt(int irq, void *id) @@ -255,10 +318,22
> @@ static int xlnx_rtc_probe(struct platform_device *pdev)
> return ret;
> }
>
> - ret = of_property_read_u32(pdev->dev.of_node, "calibration",
> - &xrtcdev->calibval);
> - if (ret)
> - xrtcdev->calibval = RTC_CALIB_DEF;
> + /* Getting the rtc_clk info */
> + xrtcdev->rtc_clk = devm_clk_get_optional(&pdev->dev, "rtc_clk");
> + if (IS_ERR(xrtcdev->rtc_clk)) {
> + if (PTR_ERR(xrtcdev->rtc_clk) != -EPROBE_DEFER)
> + dev_warn(&pdev->dev, "Device clock not found.\n");
> + }
> + xrtcdev->freq = clk_get_rate(xrtcdev->rtc_clk);
> + if (!xrtcdev->freq) {
> + ret = of_property_read_u32(pdev->dev.of_node,
> "calibration",
> + &xrtcdev->freq);
> + if (ret)
> + xrtcdev->freq = RTC_CALIB_DEF;
> + }
> + ret = readl(xrtcdev->reg_base + RTC_CALIB_RD);
> + if (!ret)
> + writel(xrtcdev->freq, (xrtcdev->reg_base + RTC_CALIB_WR));
>
> xlnx_init_rtc(xrtcdev);
>
> --
> 2.25.1
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