Message-Id: <20220724122517.1019187-1-guoren@kernel.org>
Date:   Sun, 24 Jul 2022 08:25:07 -0400
From:   guoren@...nel.org
To:     palmer@...osinc.com, heiko@...ech.de, hch@...radead.org,
        arnd@...db.de, peterz@...radead.org, will@...nel.org,
        boqun.feng@...il.com, longman@...hat.com, mingo@...hat.com,
        philipp.tomsich@...ll.eu, cmuellner@...ux.com,
        linux-kernel@...r.kernel.org, David.Laight@...LAB.COM
Cc:     linux-riscv@...ts.infradead.org, linux-csky@...r.kernel.org,
        Guo Ren <guoren@...ux.alibaba.com>
Subject: [PATCH V8 00/10] arch: Add qspinlock support with combo style

From: Guo Ren <guoren@...ux.alibaba.com>

Enable qspinlock and meet the requirements mentioned in a8ad07e5240c9
("asm-generic: qspinlock: Indicate the use of mixed-size atomics").

RISC-V LR/SC pairs could provide a strong/weak forward guarantee that
depends on micro-architecture. And RISC-V ISA spec has given out
several limitations to let hardware support strict forward guarantee
(RISC-V User ISA - 8.3 Eventual Success of Store-Conditional
Instructions):
We restricted the length of LR/SC loops to fit within 64 contiguous
instruction bytes in the base ISA to avoid undue restrictions on
instruction cache and TLB size and associativity. Similarly, we
disallowed other loads and stores within the loops to avoid restrictions
on data-cache associativity in simple implementations that track the
reservation within a private cache. The restrictions on branches and
jumps limit the time that can be spent in the sequence. Floating-point
operations and integer multiply/divide were disallowed to simplify the
operating system’s emulation of these instructions on implementations
lacking appropriate hardware support.
Software is not forbidden from using unconstrained LR/SC sequences, but
portable software must detect the case that the sequence repeatedly
fails, then fall back to an alternate code sequence that does not rely
on an unconstrained LR/SC sequence. Implementations are permitted to
unconditionally fail any unconstrained LR/SC sequence.

eg:
Some riscv hardware such as BOOMv3 & XiangShan could provide strict &
strong forward guarantee (The cache line would be kept in an exclusive
state for Backoff cycles, and only this core's interrupt could break
the LR/SC pair).
Qemu riscv give a weak forward guarantee by wrong implementation
currently [1].

Add combo spinlock (ticket & queued) support
Some architecture has a flexible requirement on the type of spinlock.
Some LL/SC architectures of ISA don't force micro-arch to give a strong
forward guarantee. Thus different kinds of memory model micro-arch would
come out in one ISA. The ticket lock is suitable for exclusive monitor
designed LL/SC micro-arch with limited cores and "!NUMA". The
queue-spinlock could deal with NUMA/large-scale scenarios with a strong
forward guarantee designed LL/SC micro-arch.

The first try of qspinlock for riscv was made in 2019.1 [2].

[1] https://github.com/qemu/qemu/blob/master/target/riscv/insn_trans/trans_rva.c.inc
[2] https://lore.kernel.org/linux-riscv/20190211043829.30096-1-michaeljclark@mac.com/#r

Changes in V8:
 - Coding convention ticket fixup
 - Move combo spinlock into riscv and simply asm-generic/spinlock.h
 - Fixup xchg16 with wrong return value
 - Add csky qspinlock
 - Add combo & qspinlock & ticket-lock comparison
 - Clean up unnecessary riscv acquire and release definitions
 - Enable ARCH_INLINE_READ*/WRITE*/SPIN* for riscv & csky

Changes in V7:
 - Add combo spinlock (ticket & queued) support
 - Rename ticket_spinlock.h
 - Remove unnecessary atomic_read in ticket_spin_value_unlocked  

Changes in V6:
 - Fixup Clang compile problem Reported-by: kernel test robot
   <lkp@...el.com>
 - Cleanup asm-generic/spinlock.h
 - Remove changelog in patch main comment part, suggested by
   Conor.Dooley@...rochip.com
 - Remove "default y if NUMA" in Kconfig

Changes in V5:
 - Update comment with RISC-V forward guarantee feature.
 - Back to V3 direction and optimize asm code.

Changes in V4:
 - Remove custom sub-word xchg implementation
 - Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32 in locking/qspinlock

Changes in V3:
 - Coding convention by Peter Zijlstra's advices

Changes in V2:
 - Coding convention in cmpxchg.h
 - Re-implement short xchg
 - Remove char & cmpxchg implementations

---

Guo Ren (2):
  asm-generic: spinlock: Move qspinlock & ticket-lock into generic spinlock.h
  riscv: Add qspinlock support

Guo Ren (5):
  asm-generic: ticket-lock: Remove unnecessary atomic_read
  asm-generic: ticket-lock: Use the same struct definitions with qspinlock
  asm-generic: ticket-lock: Move into ticket_spinlock.h
  asm-generic: spinlock: Add combo spinlock (ticket & queued)
  riscv: Add qspinlock support


Guo Ren (10):
  asm-generic: ticket-lock: Remove unnecessary atomic_read
  asm-generic: ticket-lock: Use the same struct definitions with qspinlock
  asm-generic: ticket-lock: Move into ticket_spinlock.h
  asm-generic: spinlock: Add queued spinlock support in common header
  riscv: Enable ARCH_INLINE_READ*/WRITE*/SPIN*
  riscv: atomic: Clean up unnecessary acquire and release definitions
  riscv: Add qspinlock support
  riscv: Add combo spinlock support
  csky: Enable ARCH_INLINE_READ*/WRITE*/SPIN*
  csky: Add qspinlock support

 arch/csky/Kconfig                     |  42 +++++++++
 arch/csky/include/asm/Kbuild          |   2 +
 arch/csky/include/asm/cmpxchg.h       |  20 ++++
 arch/riscv/Kconfig                    |  49 ++++++++++
 arch/riscv/include/asm/Kbuild         |   3 +-
 arch/riscv/include/asm/atomic.h       |  19 ----
 arch/riscv/include/asm/cmpxchg.h      | 129 +++-----------------------
 arch/riscv/include/asm/spinlock.h     |  77 +++++++++++++++
 arch/riscv/kernel/setup.c             |  22 +++++
 include/asm-generic/spinlock.h        |  89 +-----------------
 include/asm-generic/spinlock_types.h  |  12 +--
 include/asm-generic/ticket_spinlock.h | 103 ++++++++++++++++++++
 12 files changed, 339 insertions(+), 228 deletions(-)
 create mode 100644 arch/riscv/include/asm/spinlock.h
 create mode 100644 include/asm-generic/ticket_spinlock.h

-- 
2.36.1

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