linux-kernel - Re: [PATCH 1/2] gpio: gpio-74x164: add support for CDx4HC4094

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <CAHp75Ve4+r14dL3poOF7dCPMRgAe8etLeuBPNay0tkyNf97UWg@mail.gmail.com>
Date:   Mon, 25 Jul 2022 22:41:31 +0200
From:   Andy Shevchenko <andy.shevchenko@...il.com>
To:     Linus Walleij <linus.walleij@...aro.org>
Cc:     Marcus Folkesson <marcus.folkesson@...il.com>,
        Bartosz Golaszewski <brgl@...ev.pl>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Maxime Ripard <mripard@...nel.org>,
        "open list:GPIO SUBSYSTEM" <linux-gpio@...r.kernel.org>,
        devicetree <devicetree@...r.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 1/2] gpio: gpio-74x164: add support for CDx4HC4094

On Mon, Jul 25, 2022 at 3:54 PM Linus Walleij <linus.walleij@...aro.org> wrote:
>
> On Mon, Jul 25, 2022 at 11:32 AM Andy Shevchenko
> <andy.shevchenko@...il.com> wrote:
> > On Thu, Jul 21, 2022 at 11:32 AM Marcus Folkesson
> > <marcus.folkesson@...il.com> wrote:
> > >
> > > 74hc4094 and 75hc4094 works similar to 74x164 but has an additional
> > > storage latch associated with each stage for strobing data from the
> > > serial input to parallell buffer tri-state output.
> >
> > parallel
> >
> > > Add support for an optional strobe pin.
> >
> > Sorry for my absence of understanding, but why?
> > SPI has MOSI, CLK, CS, where the last one is exactly for that. No?
>
> Forgive me if I misunderstand, but if you use CS that
> way, the way that the SPI framework works is to assert
> CS then transfer a few chunks over SPI (MOSI/CLK)
> then de-assert CS.
>
> If CS is used for strobe, it is constantly asserted
> during transfer and the sequence will be latched
> out immediately as you write the SPI transfers and
> the data is clocked through the register, making the
> whole train of zeroes and ones flash across the
> output pins before they stabilize after the SPI
> transfer is finished.
>
> If you first do the SPI transfer, then strobe after
> finished, this will not happen.
>
> Then it should be a separate pin, so this doesn't
> happen, right?
>
> Yours,
> Linus Walleij



-- 
With Best Regards,
Andy Shevchenko