linux-kernel - Re: [PATCH 6/6] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC

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Message-ID: <8fcd765c-d0af-9759-be0c-8ac90e4e5d95@microchip.com>
Date:   Tue, 26 Jul 2022 18:53:32 +0000
From:   <Conor.Dooley@...rochip.com>
To:     <prabhakar.mahadev-lad.rj@...renesas.com>,
        <geert+renesas@...der.be>, <magnus.damm@...il.com>,
        <robh+dt@...nel.org>, <krzysztof.kozlowski+dt@...aro.org>,
        <paul.walmsley@...ive.com>, <palmer@...belt.com>,
        <aou@...s.berkeley.edu>
CC:     <anup@...infault.org>, <linux-renesas-soc@...r.kernel.org>,
        <devicetree@...r.kernel.org>, <linux-riscv@...ts.infradead.org>,
        <linux-kernel@...r.kernel.org>, <prabhakar.csengg@...il.com>,
        <biju.das.jz@...renesas.com>
Subject: Re: [PATCH 6/6] riscv: dts: renesas: Add initial devicetree for
 Renesas RZ/Five SoC

On 26/07/2022 19:25, Conor.Dooley@...rochip.com wrote:
> Hey,
> Saw your other binding patches coming in earlier & wondered if
> this would show up today ;)
> 
> On 26/07/2022 19:06, Lad Prabhakar wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>> Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP
>> Single).
>>
>> Below is the list of IP blocks added in the initial SoC DTSI which can be
>> used to boot via initramfs on RZ/Five SMARC EVK:
>> - AX45MP CPU
>> - CPG
>> - PINCTRL
>> - PLIC
>> - SCIF0
>> - SYSC
>>
>> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
>> ---
>>  arch/riscv/boot/dts/Makefile               |   1 +
>>  arch/riscv/boot/dts/renesas/r9a07g043.dtsi | 121 +++++++++++++++++++++
> 
> Missing files? Where is your Makefile for this directory?
> Or the board dts?
> 
> Enabling CONFIG_SOC_RENESAS_RZFIVE causes dtbs_check to fail :(
> 

FWIW, it breaks the dts build too even disabled b/c of the missing
Makefile.
Thanks,
Conor.