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Message-ID: <c923758d-b591-26bf-8091-527500ae7a6f@collabora.com>
Date: Tue, 26 Jul 2022 10:54:38 +0200
From: AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>
To: Chukun Pan <amadeus@....edu.cn>,
Matthias Brugger <matthias.bgg@...il.com>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org, Rex-BC Chen <rex-bc.chen@...iatek.com>
Subject: Re: [PATCH 2/3] soc: mediatek: update power domain data of MT7623A
Il 26/07/22 05:06, Chukun Pan ha scritto:
> When running OpenWrt on MT7623A, I receive a kernel
> warning as follows (Device dts using mt7623.dtsi):
>
> mtk-scpsys 10006000.scpsys: Failed to power on domain mfg
> WARNING: CPU: 0 PID: 1 at drivers/soc/mediatek/mtk-scpsys.c:457 0xc04a4130
>
> When I switch the device dts to using mt7623a.dtsi,
> the system fails to boot:
>
> rcu: INFO: rcu_preempt detected stalls on CPUs/tasks:
> rcu: 0-...0: (0 ticks this GP) idle=146/1/0x40000000 softirq=53/53 fqs=1051
> (detected by 1, t=2102 jiffies, g=-1111, q=18)
> Sending NMI from CPU 1 to CPUs 0:
>
> Solved the problem by duplicating the power domain of
> the MT7623 (except MFG) to MT7623A, the system works
> fine without kernel warnings/errors.
>
> Signed-off-by: Chukun Pan <amadeus@....edu.cn>
Can anyone from MediaTek check if these power domains do exist on MT7623A?
Thanks,
Angelo
> ---
> drivers/soc/mediatek/mtk-scpsys.c | 35 +++++++++++++++++++++++++++++++
> 1 file changed, 35 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
> index ca75b14931ec..8b5713db1ca3 100644
> --- a/drivers/soc/mediatek/mtk-scpsys.c
> +++ b/drivers/soc/mediatek/mtk-scpsys.c
> @@ -910,6 +910,41 @@ static const struct scp_domain_data scp_domain_data_mt7623a[] = {
> .clk_id = {CLK_NONE},
> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> },
> + [MT7623A_POWER_DOMAIN_VDEC] = {
> + .name = "vdec",
> + .sta_mask = PWR_STATUS_VDEC,
> + .ctl_offs = SPM_VDE_PWR_CON,
> + .sram_pdn_bits = GENMASK(11, 8),
> + .sram_pdn_ack_bits = GENMASK(12, 12),
> + .clk_id = {CLK_MM},
> + .caps = MTK_SCPD_ACTIVE_WAKEUP,
> + },
> + [MT7623A_POWER_DOMAIN_DISP] = {
> + .name = "disp",
> + .sta_mask = PWR_STATUS_DISP,
> + .ctl_offs = SPM_DIS_PWR_CON,
> + .sram_pdn_bits = GENMASK(11, 8),
> + .clk_id = {CLK_MM},
> + .bus_prot_mask = MT2701_TOP_AXI_PROT_EN_MM_M0,
> + .caps = MTK_SCPD_ACTIVE_WAKEUP,
> + },
> + [MT7623A_POWER_DOMAIN_ISP] = {
> + .name = "isp",
> + .sta_mask = PWR_STATUS_ISP,
> + .ctl_offs = SPM_ISP_PWR_CON,
> + .sram_pdn_bits = GENMASK(11, 8),
> + .sram_pdn_ack_bits = GENMASK(13, 12),
> + .clk_id = {CLK_MM},
> + .caps = MTK_SCPD_ACTIVE_WAKEUP,
> + },
> + [MT7623A_POWER_DOMAIN_BDP] = {
> + .name = "bdp",
> + .sta_mask = PWR_STATUS_BDP,
> + .ctl_offs = SPM_BDP_PWR_CON,
> + .sram_pdn_bits = GENMASK(11, 8),
> + .clk_id = {CLK_NONE},
> + .caps = MTK_SCPD_ACTIVE_WAKEUP,
> + },
> };
>
> /*
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