linux-kernel - Re: [PATCH v13 3/3] mmc: mediatek: add support for SDIO eint wakup IRQ

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Message-ID: <aface69bc8eeb0a34805428fa36d13f7909f694d.camel@mediatek.com>
Date:   Tue, 26 Jul 2022 15:46:34 +0800
From:   Axe Yang <axe.yang@...iatek.com>
To:     Linus Walleij <linus.walleij@...aro.org>,
        Ulf Hansson <ulf.hansson@...aro.org>
CC:     Rob Herring <robh+dt@...nel.org>,
        Chaotian Jing <chaotian.jing@...iatek.com>,
        Matthias Brugger <matthias.bgg@...il.com>,
        Adrian Hunter <adrian.hunter@...el.com>,
        Yoshihiro Shimoda <yoshihiro.shimoda.uh@...esas.com>,
        Satya Tangirala <satyat@...gle.com>,
        Andy Shevchenko <andriy.shevchenko@...ux.intel.com>,
        Wolfram Sang <wsa+renesas@...g-engineering.com>,
        Lucas Stach <dev@...xeye.de>,
        "Eric Biggers" <ebiggers@...gle.com>,
        Andrew Jeffery <andrew@...id.au>,
        "Stephen Boyd" <swboyd@...omium.org>,
        Kiwoong Kim <kwmad.kim@...sung.com>,
        Yue Hu <huyue2@...ong.com>, Tian Tao <tiantao6@...ilicon.com>,
        <angelogioacchino.delregno@...labora.com>,
        <linux-mmc@...r.kernel.org>, <devicetree@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-mediatek@...ts.infradead.org>,
        <Project_Global_Chrome_Upstream_Group@...iatek.com>,
        Yong Mao <yong.mao@...iatek.com>
Subject: Re: [PATCH v13 3/3] mmc: mediatek: add support for SDIO eint wakup
 IRQ

On Mon, 2022-07-25 at 14:46 +0200, Linus Walleij wrote:
> On Mon, Jul 25, 2022 at 11:13 AM Axe Yang <axe.yang@...iatek.com>
> wrote:
> > On Fri, 2022-07-22 at 13:21 +0200, Linus Walleij wrote:
> > > On Thu, Jun 23, 2022 at 11:10 AM Axe Yang <axe.yang@...iatek.com>
> > > wrote:
> > SDIO DAT1 pin mode is changed to GPIO mode in
> > dev_pm_set_dedicated_wake_irq_reverse():
> > 
> > 
https://urldefense.com/v3/__https://elixir.bootlin.com/linux/latest/source/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c*L339__;Iw!!CTRNKA9wMg0ARbw!zE3kmi37pZw4HiBNeRipWbi3gbAqrljLVQc5JVz-WP_NaIWTVhXshkakjFNh478e$
> >  
> > 
> > dev_pm_set_dedicated_wake_irq_reverse() -> ...
> > ->request_threaded_irq()
> > -> __setup_irq() -> irq_request_resources() ->
> > mtk_eint_irq_request_resources()-> mtk_xt_set_gpio_as_eint()
> 
> This doesn't seem to have much to do with pin control?
> No pin control functions are called on this execution path,
> no pin control state is changed, right?

That's right, no pin control state is changed.

> 
> If what you mean is that
> it happens to poke into the same hardware registers that is
> mainly a matter of concurrency in the driver, sometimes two
> abstractions happen to have to poke into the same hardware
> registers and then it is up to the driver to maintain state for
> the hardware, this is not a question for the framework.
> 
> How is Mediatek developers thinking about this thing in general?
> You are a few people who developed the driver so certainly
> you must have some design idea to why irq_request_resources()
> poke around in these registers? Does it even perform pin
> control behind the back of the pin control framework?

I see. It is sensible to reset pin function to GPIO mode when trying to
register the pin to eint mode, and the operation is out of pinctrl
framework.

Seems like maintain the pin state in driver is the only way to fix the
pin function conflict.

> 
> > To restore SDIO DAT1 pin to uhs mode. I have to call
> > pinctrl_select_state() twice(change pinctrl to another state, then
> > change back to uhs mode). Ulf worried we might be doing something
> > at
> > the mmc driver level, which should really be managed at the pinctrl
> > layer.
> > 
> > Do you have any comment or suggestion on this?
> 
> The pin control state transitions are really just finite automata.
> 
> Your pin control needs to be different when using wakeup from
> when being used for SDIO and this is perfectly fine, it's no
> different from the fact that the regulator and clock might need
> to be in different states, so I don't quite understand the
> question?

I see. At first I thought that pinctrl framework should be aware of
the hidden modification of pin function. But as you said, it is just
a finite automata. Driver should correct GPIO settings by itself if pin
state be changed outside pin control state mechanical.
Sorry for the noise, and thanks for your comment again.

> 
> 
Regards,
Axe