[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-Id: <20220726170725.3245278-2-mail@conchuod.ie>
Date: Tue, 26 Jul 2022 18:07:25 +0100
From: Conor Dooley <mail@...chuod.ie>
To: Linus Walleij <linus.walleij@...aro.org>,
Bartosz Golaszewski <brgl@...ev.pl>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Palmer Dabbelt <palmer@...belt.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Albert Ou <aou@...s.berkeley.edu>,
Conor Dooley <conor.dooley@...rochip.com>,
Atul Khare <atulkhare@...osinc.com>,
Sagar Kadam <sagar.kadam@...ive.com>
Cc: linux-gpio@...r.kernel.org, devicetree@...r.kernel.org,
linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: [PATCH v3 1/2] dt-bindings: sifive: add cache-set value of 2048
From: Atul Khare <atulkhare@...osinc.com>
Fixes Running device tree schema validation error messages like
'... cache-sets:0:0: 1024 was expected'.
The existing bindings had a single enumerated value of 1024, which
trips up the dt-schema checks. The ISA permits any arbitrary power
of two for the cache-sets value, but we decided to add the single
additional value of 2048 because we couldn't spot an obvious way
to express the constraint in the schema.
Signed-off-by: Atul Khare <atulkhare@...osinc.com>
Signed-off-by: Conor Dooley <conor.dooley@...rochip.com>
---
Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
index e2d330bd4608..ab6043d9cdbe 100644
--- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
+++ b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
@@ -46,7 +46,7 @@ properties:
const: 2
cache-sets:
- const: 1024
+ enum: [1024, 2048]
cache-size:
const: 2097152
--
2.37.1
Powered by blists - more mailing lists