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Message-ID: <OS0PR01MB5922763582B836DA45CDFF0886979@OS0PR01MB5922.jpnprd01.prod.outlook.com>
Date:   Wed, 27 Jul 2022 12:21:15 +0000
From:   Biju Das <biju.das.jz@...renesas.com>
To:     Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
        "Lad, Prabhakar" <prabhakar.csengg@...il.com>
CC:     Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@...renesas.com>,
        Geert Uytterhoeven <geert+renesas@...der.be>,
        Magnus Damm <magnus.damm@...il.com>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Palmer Dabbelt <palmer@...belt.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        Anup Patel <anup@...infault.org>,
        Linux-Renesas <linux-renesas-soc@...r.kernel.org>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@...r.kernel.org>,
        linux-riscv <linux-riscv@...ts.infradead.org>,
        LKML <linux-kernel@...r.kernel.org>
Subject: RE: [PATCH 4/6] dt-bindings: riscv: Add DT binding documentation for
 Renesas RZ/Five SoC and SMARC EVK

Hi,

> Subject: Re: [PATCH 4/6] dt-bindings: riscv: Add DT binding
> documentation for Renesas RZ/Five SoC and SMARC EVK
> 
> On 27/07/2022 13:37, Lad, Prabhakar wrote:
> >>>>
> >>> I did run the dtbs_check test as per your suggestion (below is the
> >>> log) and didn't see "no matching schema error"
> >>>
> >>
> >> So you do not see any errors at all. Then it does not work, does it?
> >>
> > Right I reverted my changes I can see it complaining, dtb_check seems
> > to have returned false positive in my case.
> >
> > What approach would you suggest to ignore the schema here?
> 
> I don't think currently it would work with your approach. Instead, you
> should select here all SoCs which the schema should match.
> 
> This leads to my previous concern - you use the same SoC compatible for
> two different architectures and different SoCs: ARMv8 and RISC-V.

Or is it same SoC(R9A07G043) based on two different CPU architectures (ARMv8 and RISC-V)
Using same SoM and Carrier board?

Cheers,
Biju

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