lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Wed, 27 Jul 2022 16:32:28 +0100
From:   "Lad, Prabhakar" <prabhakar.csengg@...il.com>
To:     Conor.Dooley@...rochip.com
Cc:     Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
        Biju Das <biju.das.jz@...renesas.com>,
        "Lad, Prabhakar" <prabhakar.mahadev-lad.rj@...renesas.com>,
        Geert Uytterhoeven <geert+renesas@...der.be>,
        Magnus Damm <magnus.damm@...il.com>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Palmer Dabbelt <palmer@...belt.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        Anup Patel <anup@...infault.org>,
        Linux-Renesas <linux-renesas-soc@...r.kernel.org>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@...r.kernel.org>,
        linux-riscv <linux-riscv@...ts.infradead.org>,
        LKML <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 4/6] dt-bindings: riscv: Add DT binding documentation for
 Renesas RZ/Five SoC and SMARC EVK

On Wed, Jul 27, 2022 at 2:29 PM <Conor.Dooley@...rochip.com> wrote:
>
> On 27/07/2022 14:00, Krzysztof Kozlowski wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
> > On 27/07/2022 14:56, Biju Das wrote:
> >>>
> >>> Then it is not the same SoC! Same means same, identical. CPU
> >>> architecture is one of the major differences, which means it is not the
> >>> same.
> >>
> >> Family SoC(R9A07G043) is at top level. Then it has different SoCId for taking care of
> >> differences for SoC based on ARMV8 and RISC-V which has separate compatible like
> >> r9a07g043u11 and r9a07g043f01?
> >
> > This does not answer the concern - it's not the same SoC. The most
> > generic compatible denotes the most common part. I would argue that
> > instruction set and architecture are the most important differences.
> > None of ARMv8 SoCs (SoCs, not CPU cores) have "arm,armv8" compatible and
> > you went even more - you combined two architectures in the most generic
> > compatibles.
>
> I would have to agree with this. The most "core" part of the SoC is
> its architecture and while the peripheral IPs might be the same etc
> & the Renesas marketing team might have put them in the same "family",
> for the purposes of a device tree I don't see how having a common
> fallback makes sense.
>
Agreed, I was following the same which we have done on the ARM64 schema.

I am waiting on Geert's feedback on whether we should follow as
Krzysztof suggested ie to have

renesas,smarc-evk-r9a07g043f01 - for the board
renesas,9a07g043f01 - for the SoC

Cheers,
Prabhakar

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ