linux-kernel - Re: [PATCH V2 0/3] Add S4 SoC clock controller driver

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Date:   Thu, 28 Jul 2022 16:06:25 +0800
From:   Yu Tu <yu.tu@...ogic.com>
To:     Jerome Brunet <jbrunet@...libre.com>, <linux-clk@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-amlogic@...ts.infradead.org>,
        <linux-kernel@...r.kernel.org>, <devicetree@...r.kernel.org>,
        Rob Herring <robh+dt@...nel.org>,
        Neil Armstrong <narmstrong@...libre.com>,
        Kevin Hilman <khilman@...libre.com>,
        Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Martin Blumenstingl <martin.blumenstingl@...glemail.com>
Subject: Re: [PATCH V2 0/3] Add S4 SoC clock controller driver

Hi JB，

On 2022/7/28 15:08, Jerome Brunet wrote:
> [ EXTERNAL EMAIL ]
> 
> 
> On Thu 28 Jul 2022 at 13:41, Yu Tu <yu.tu@...ogic.com> wrote:
> 
>> 1. Add clock controller driver for S4 SOC.
>>
>> Yu Tu (3):
>>    dt-bindings: clk: meson: add S4 SoC clock controller bindings
>>    arm64: dts: meson: add S4 Soc clock controller in DT
>>    clk: meson: s4: add s4 SoC clock controller driver
>>
>> V1 -> V2: Change format as discussed in the email.
>>
>> Link:https://lore.kernel.org/linux-amlogic/20220708062757.3662-1-yu.tu@amlogic.com/
>>
>>   .../bindings/clock/amlogic,gxbb-clkc.txt      |    1 +
>>   MAINTAINERS                                   |    1 +
>>   arch/arm64/boot/dts/amlogic/meson-s4.dtsi     |   11 +
>>   drivers/clk/meson/Kconfig                     |   15 +
>>   drivers/clk/meson/Makefile                    |    1 +
>>   drivers/clk/meson/s4.c                        | 4732 +++++++++++++++++
>>   drivers/clk/meson/s4.h                        |  296 ++
>>   include/dt-bindings/clock/s4-clkc.h           |  146 +
>>   8 files changed, 5203 insertions(+)
>>   create mode 100644 drivers/clk/meson/s4.c
>>   create mode 100644 drivers/clk/meson/s4.h
>>   create mode 100644 include/dt-bindings/clock/s4-clkc.h
>>
>>
>> base-commit: b293bc9286ee21824e93f0fcfed3b78fdfee01e6
> 
> Please don't post until you have addressed *ALL* the comments from the
> previous version.
The last email asked you to adopt A1 method, but you did not reply?

> 
> At first glance, I can see that this is still a single driver for
> what is obviously 2 controllers with 2 register spaces. Simple comments
> like the "<< 2" in the register declaration have not been addressed either.
I understand that this should be a controller, just two address 
descriptions. One is the various PLL registers and one is the clock for 
the peripherals. And PLL is to provide a clock source for various 
peripheral clocks. So a clock controller is reasonable. I think you got 
it wrong.

Ok, if you insist on using two clock controllers,, please provide your 
the reason and example code?

> 
> Seeing that, I have not reviewed this version further.
> I won't until all the comments from v1 are either addressed or answer
> 
> Regards
> Jerome
> 
> .