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Message-ID: <165900506117.15455.179308820042682784.tip-bot2@tip-bot2>
Date: Thu, 28 Jul 2022 10:44:21 -0000
From: "tip-bot2 for Thomas Gleixner" <tip-bot2@...utronix.de>
To: linux-tip-commits@...r.kernel.org
Cc: x86@...nel.org, linux-kernel@...r.kernel.org
Subject: [tip: timers/core] Merge tag 'timers-v5.20-rc1' of
https://git.linaro.org/people/daniel.lezcano/linux into timers/core
The following commit has been merged into the timers/core branch of tip:
Commit-ID: 75fed76ebc8f75e7a9f8c9ca39482aa34932ad41
Gitweb: https://git.kernel.org/tip/75fed76ebc8f75e7a9f8c9ca39482aa34932ad41
Author: Thomas Gleixner <tglx@...utronix.de>
AuthorDate: Thu, 28 Jul 2022 12:33:34 +02:00
Committer: Thomas Gleixner <tglx@...utronix.de>
CommitterDate: Thu, 28 Jul 2022 12:33:34 +02:00
Merge tag 'timers-v5.20-rc1' of https://git.linaro.org/people/daniel.lezcano/linux into timers/core
Pull clockevent/source updates from Daniel Lezcano:
- Add the missing DT bindings for the MTU nomadik timer (Linus
Walleij)
- Fix grammar typo in the ARM global timer Kconfig option (Randy
Dunlap)
- Add the tegra186 timer and use it on the tegra234 board (Thierry
Reding)
- Add the 'CPUXGPT' CPU timer for Mediatek MT6795 and implement a
workaround to overcome an ATF bug where the timer is not correctly
initialized (AngeloGioacchino Del Regno)
- Rework the suspend/resume approach to enable the feature on the
timer even it is not an active clock and fix a compilation warning
(Claudiu Beznea)
- Add the Add R-Car Gen4 timer support along with the DT bindings
(Wolfram Sang)
- Add compatible for ti,am654-timer to support AM6 SoC (Tony Lindgren)
- Fix Kconfig option to put it back to 'bool' instead of 'tristate'
for the tegra186 (Daniel Lezcano)
- Sort 'family,type' DT bindings for the Renesas timers (Geert
Uytterhoeven)
- Add compatible 'allwinner,sun20i-d1-timer' for Allwinner D1 (Samuel
Holland)
- Remove unnecessary (void*) conversions for sun4i (XU pengfei)
- Remove unnecessary (void*) conversions for sun5i (Li zeming)
Link: https://lore.kernel.org/all/7472984e-f502-5f27-82bf-070127dd85a5@linaro.org
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