lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
Open Source and information security mailing list archives
| ||
|
Date: Thu, 28 Jul 2022 17:34:14 +0300 From: Serge Semin <Sergey.Semin@...kalelectronics.ru> To: Rob Herring <robh+dt@...nel.org>, Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>, Bjorn Helgaas <bhelgaas@...gle.com>, Lorenzo Pieralisi <lorenzo.pieralisi@....com>, Jingoo Han <jingoohan1@...il.com>, Gustavo Pimentel <gustavo.pimentel@...opsys.com> CC: Serge Semin <Sergey.Semin@...kalelectronics.ru>, Serge Semin <fancer.lancer@...il.com>, Alexey Malahov <Alexey.Malahov@...kalelectronics.ru>, Pavel Parkhomenko <Pavel.Parkhomenko@...kalelectronics.ru>, Krzysztof WilczyĆski <kw@...ux.com>, Frank Li <Frank.Li@....com>, Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>, <linux-pci@...r.kernel.org>, <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org> Subject: [PATCH v4 04/17] dt-bindings: PCI: dwc: Add max-link-speed common property In accordance with [1] DW PCIe controllers support up to Gen5 link speed. Let's add the max-link-speed property upper bound to 5 then. The DT bindings of the particular devices are expected to setup more strict constraint on that parameter. [1] Synopsys DesignWare Cores PCI Express Controller Databook, Version 5.40a, March 2019, p. 27 Signed-off-by: Serge Semin <Sergey.Semin@...kalelectronics.ru> --- Changelog v3: - This is a new patch unpinned from the next one: https://lore.kernel.org/linux-pci/20220503214638.1895-2-Sergey.Semin@baikalelectronics.ru/ by the Rob' request. (@Rob) --- Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml | 3 +++ Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml | 2 ++ Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml | 1 + 3 files changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml index 627a5d6625ba..b2fbe886981b 100644 --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml @@ -45,6 +45,9 @@ properties: the peripheral devices available on the PCIe bus. maxItems: 1 + max-link-speed: + maximum: 5 + num-lanes: description: Number of PCIe link lanes to use. Can be omitted should the already diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml index dcd521aed213..fc3b5d4ac245 100644 --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml @@ -55,4 +55,6 @@ examples: phys = <&pcie_phy0>, <&pcie_phy1>, <&pcie_phy2>, <&pcie_phy3>; phy-names = "pcie0", "pcie1", "pcie2", "pcie3"; + + max-link-speed = <3>; }; diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml index 4a5c8b933b52..01cedf51e0f8 100644 --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml @@ -74,4 +74,5 @@ examples: phy-names = "pcie"; num-lanes = <1>; + max-link-speed = <3>; }; -- 2.35.1
Powered by blists - more mailing lists