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Message-ID: <20220729063208.16799-18-tinghan.shen@mediatek.com>
Date: Fri, 29 Jul 2022 14:32:05 +0800
From: Tinghan Shen <tinghan.shen@...iatek.com>
To: Yong Wu <yong.wu@...iatek.com>, Joerg Roedel <joro@...tes.org>,
Will Deacon <will@...nel.org>,
Robin Murphy <robin.murphy@....com>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Lee Jones <lee@...nel.org>,
Matthias Brugger <matthias.bgg@...il.com>,
Tinghan Shen <tinghan.shen@...iatek.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>,
MandyJH Liu <mandyjh.liu@...iatek.com>
CC: <iommu@...ts.linux.dev>, <linux-mediatek@...ts.infradead.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<Project_Global_Chrome_Upstream_Group@...iatek.com>,
Trevor Wu <trevor.wu@...iatek.com>
Subject: [PATCH v4 17/20] arm64: dts: mt8195: Specify audio reset controller
From: Trevor Wu <trevor.wu@...iatek.com>
Specify audio reset controller for audio hardware resetting.
Signed-off-by: Trevor Wu <trevor.wu@...iatek.com>
Signed-off-by: Tinghan Shen <tinghan.shen@...iatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index f42d33414125f..9c14c42f07139 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -680,6 +680,7 @@
"mediatek,mt6589-wdt";
mediatek,disable-extrst;
reg = <0 0x10007000 0 0x100>;
+ #reset-cells = <1>;
};
apmixedsys: syscon@...0c000 {
@@ -782,6 +783,8 @@
mediatek,topckgen = <&topckgen>;
power-domains = <&spm MT8195_POWER_DOMAIN_AUDIO>;
interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>;
+ resets = <&watchdog 14>;
+ reset-names = "audiosys";
clocks = <&clk26m>,
<&apmixedsys CLK_APMIXED_APLL1>,
<&apmixedsys CLK_APMIXED_APLL2>,
--
2.18.0
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