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Message-Id: <20220729015029.14863-2-william.zhang@broadcom.com>
Date: Thu, 28 Jul 2022 18:50:27 -0700
From: William Zhang <william.zhang@...adcom.com>
To: Linux ARM List <linux-arm-kernel@...ts.infradead.org>
Cc: Broadcom Kernel List <bcm-kernel-feedback-list@...adcom.com>,
kursad.oney@...adcom.com, dan.beygelman@...adcom.com,
f.fainelli@...il.com, anand.gore@...adcom.com,
joel.peshkin@...adcom.com,
William Zhang <william.zhang@...adcom.com>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Rob Herring <robh+dt@...nel.org>, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: [PATCH 2/4] ARM: dts: bcmbca: fix interrupt controller properties
Add the missing gic registers and interrupts property to the gic node
for BCM63178 and BCM6846.
Fixes: fc85b7e64acb ("ARM: dts: add dts files for bcmbca soc 63178")
Fixes: de1a99ac0b64 ("ARM: dts: Add DTS files for bcmbca SoC BCM6846")
Signed-off-by: William Zhang <william.zhang@...adcom.com>
---
arch/arm/boot/dts/bcm63178.dtsi | 8 +++++---
arch/arm/boot/dts/bcm6846.dtsi | 8 +++++---
2 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/bcm63178.dtsi b/arch/arm/boot/dts/bcm63178.dtsi
index 14d2c5bd2c52..202baa3a5e74 100644
--- a/arch/arm/boot/dts/bcm63178.dtsi
+++ b/arch/arm/boot/dts/bcm63178.dtsi
@@ -88,15 +88,17 @@ axi@...00000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
- ranges = <0 0x81000000 0x4000>;
+ ranges = <0 0x81000000 0x8000>;
gic: interrupt-controller@...0 {
compatible = "arm,cortex-a7-gic";
#interrupt-cells = <3>;
- #address-cells = <0>;
interrupt-controller;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_HIGH)>;
reg = <0x1000 0x1000>,
- <0x2000 0x2000>;
+ <0x2000 0x2000>,
+ <0x4000 0x2000>,
+ <0x6000 0x2000>;
};
};
diff --git a/arch/arm/boot/dts/bcm6846.dtsi b/arch/arm/boot/dts/bcm6846.dtsi
index b74491a3f111..93b44283b9ba 100644
--- a/arch/arm/boot/dts/bcm6846.dtsi
+++ b/arch/arm/boot/dts/bcm6846.dtsi
@@ -73,15 +73,17 @@ axi@...00000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
- ranges = <0 0x81000000 0x4000>;
+ ranges = <0 0x81000000 0x8000>;
gic: interrupt-controller@...0 {
compatible = "arm,cortex-a7-gic";
#interrupt-cells = <3>;
- #address-cells = <0>;
interrupt-controller;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
reg = <0x1000 0x1000>,
- <0x2000 0x2000>;
+ <0x2000 0x2000>,
+ <0x4000 0x2000>,
+ <0x6000 0x2000>;
};
};
--
2.34.1
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