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Date: Fri, 29 Jul 2022 12:18:25 -0500 From: Bjorn Helgaas <helgaas@...nel.org> To: Krishna chaitanya chundru <quic_krichai@...cinc.com> Cc: linux-pci@...r.kernel.org, linux-arm-msm@...r.kernel.org, linux-kernel@...r.kernel.org, mka@...omium.org, quic_vbadigan@...cinc.com, quic_hemantk@...cinc.com, quic_nitegupt@...cinc.com, quic_skananth@...cinc.com, quic_ramkri@...cinc.com, manivannan.sadhasivam@...aro.org, swboyd@...omium.org, dmitry.baryshkov@...aro.org, Stanimir Varbanov <svarbanov@...sol.com>, Andy Gross <agross@...nel.org>, Bjorn Andersson <bjorn.andersson@...aro.org>, Lorenzo Pieralisi <lpieralisi@...nel.org>, Rob Herring <robh@...nel.org>, Krzysztof WilczyĆski <kw@...ux.com>, Bjorn Helgaas <bhelgaas@...gle.com> Subject: Re: [PATCH v3] PCI: qcom: Allow L1 and its sub states On Fri, Jul 15, 2022 at 05:29:25PM +0530, Krishna chaitanya chundru wrote: > Allow L1 and its sub-states in the qcom pcie driver. > By default this is disabled in the qcom specific hardware. > So enabling it explicitly only for controllers belonging to > 2_7_0. > > This patch will not affect any link capability registers, this > will allow the link transitions to L1 and its sub states only > if they are already supported. > > Signed-off-by: Krishna chaitanya chundru <quic_krichai@...cinc.com> > Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org> Applied to pci/ctrl/qcom for v5.20, thanks! > ---- > > Changes since v1 & v2: > - Update in the commit text only. > --- > drivers/pci/controller/dwc/pcie-qcom.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index a7202f0..5ef444f 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > @@ -41,6 +41,9 @@ > #define L23_CLK_RMV_DIS BIT(2) > #define L1_CLK_RMV_DIS BIT(1) > > +#define PCIE20_PARF_PM_CTRL 0x20 > +#define REQ_NOT_ENTR_L1 BIT(5) > + > #define PCIE20_PARF_PHY_CTRL 0x40 > #define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK GENMASK(20, 16) > #define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) ((x) << 16) > @@ -1261,6 +1264,11 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) > val |= BIT(4); > writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL); > > + /* Enable L1 and L1ss */ > + val = readl(pcie->parf + PCIE20_PARF_PM_CTRL); > + val &= ~REQ_NOT_ENTR_L1; > + writel(val, pcie->parf + PCIE20_PARF_PM_CTRL); > + > if (IS_ENABLED(CONFIG_PCI_MSI)) { > val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT); > val |= BIT(31); > -- > 2.7.4 >
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