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Message-ID: <20220801175654.GA1257218-robh@kernel.org>
Date: Mon, 1 Aug 2022 11:56:54 -0600
From: Rob Herring <robh@...nel.org>
To: Serge Semin <Sergey.Semin@...kalelectronics.ru>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
linux-pci@...r.kernel.org, linux-kernel@...r.kernel.org,
Krzysztof WilczyĆski <kw@...ux.com>,
Frank Li <Frank.Li@....com>, devicetree@...r.kernel.org,
Alexey Malahov <Alexey.Malahov@...kalelectronics.ru>,
Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>,
Bjorn Helgaas <bhelgaas@...gle.com>,
Jingoo Han <jingoohan1@...il.com>,
Serge Semin <fancer.lancer@...il.com>,
Pavel Parkhomenko <Pavel.Parkhomenko@...kalelectronics.ru>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
Gustavo Pimentel <gustavo.pimentel@...opsys.com>
Subject: Re: [PATCH v4 04/17] dt-bindings: PCI: dwc: Add max-link-speed
common property
On Thu, 28 Jul 2022 17:34:14 +0300, Serge Semin wrote:
> In accordance with [1] DW PCIe controllers support up to Gen5 link speed.
> Let's add the max-link-speed property upper bound to 5 then. The DT
> bindings of the particular devices are expected to setup more strict
> constraint on that parameter.
>
> [1] Synopsys DesignWare Cores PCI Express Controller Databook, Version
> 5.40a, March 2019, p. 27
>
> Signed-off-by: Serge Semin <Sergey.Semin@...kalelectronics.ru>
>
> ---
>
> Changelog v3:
> - This is a new patch unpinned from the next one:
> https://lore.kernel.org/linux-pci/20220503214638.1895-2-Sergey.Semin@baikalelectronics.ru/
> by the Rob' request. (@Rob)
> ---
> Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml | 3 +++
> Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml | 2 ++
> Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml | 1 +
> 3 files changed, 6 insertions(+)
>
Reviewed-by: Rob Herring <robh@...nel.org>
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