linux-kernel - Re: [PATCH 1/2] spi: dt-binding: add Microchip CoreQSPI compatible

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <CAH_iE_03fHMbCwGPsE_CmbokRh5cW_bEaX8RodK1ovWeTSHuhQ@mail.gmail.com>
Date:   Mon, 1 Aug 2022 16:22:16 +0530
From:   naga sureshkumar <nagasuresh12@...il.com>
To:     Conor.Dooley@...rochip.com
Cc:     Nagasuresh.Relli@...rochip.com, broonie@...nel.org,
        robh+dt@...nel.org, krzysztof.kozlowski+dt@...aro.org,
        linux-spi@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH 1/2] spi: dt-binding: add Microchip CoreQSPI compatible

Hi Conor,

Thanks for your review.

On Mon, Aug 1, 2022 at 3:54 PM <Conor.Dooley@...rochip.com> wrote:
>
> Hey Suresh,
>
> On 01/08/2022 10:42, Naga Sureshkumar Relli wrote:
> > Add compatible string for Microchip CoreQSPI controller.
> >
> > Signed-off-by: Naga Sureshkumar Relli <nagasuresh.relli@...rochip.com>
> > ---
> >  .../devicetree/bindings/spi/microchip,mpfs-spi.yaml    | 10 +++++++---
> >  1 file changed, 7 insertions(+), 3 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml b/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
> > index 7326c0a28d16..b65f4e070796 100644
> > --- a/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
> > +++ b/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
> > @@ -14,9 +14,13 @@ allOf:
> >
> >  properties:
> >    compatible:
> > -    enum:
> > -      - microchip,mpfs-spi
> > -      - microchip,mpfs-qspi
> > +    oneOf:
> > +      - description: Microchip's Polarfire SoC SPI controller.
>                                          ^
> (This is a capital F btw)
>
> > +        const: microchip,mpfs-spi
> > +      - description: Microchip's Polarfire SoC QSPI controller.
> > +        const: microchip,mpfs-qspi
> > +      - description: Microchip's FPGA QSPI controller.
> > +        const: microchip,coreqspi-rtl-v2
>
> I am not sure that this is the correct "hierarchy". coreQSPI has a
> subset of the registers of the "hard" QSPI & the same driver works
> for both at the moment. The "hard" QSPI is based on the FPGA core,
> so I think this should be changed to something like the following:
I have added each element for each controller separately.
but the below one hierarchy explains clearly about the cores.
I will update the bindings.
>
> properties:
>   compatible:
>     oneOf:
>       - description: Microchip's PolarFire SoC QSPI controller
>         items:
>           - const: microchip,mpfs-qspi
>           - const: microchip,coreqspi-rtl-v2
>       - description: Microchip's fabric based QSPI IP core
>         const: microchip,coreqspi-rtl-v2
>       - description: Microchip's PolarFire SoC SPI controller
>         const: microchip,mpfs-spi
>
> Unrelated to this patch, but a
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index f4202a19faa1..887bfee5c7af 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -17526,6 +17526,7 @@ F:      drivers/pci/controller/pcie-microchip-host.c
>  F:     drivers/rtc/rtc-mpfs.c
>  F:     drivers/soc/microchip/
>  F:     drivers/spi/spi-microchip-core.c
> +F:     drivers/spi/spi-microchip-core-qspi.c
>  F:     drivers/usb/musb/mpfs.c
>  F:     include/soc/microchip/mpfs.h
>
> Would be nice too.
Ok.

Thanks,
Naga Sureshkumar Relli.
>
> Thanks,
> Conor.