| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Date: Wed, 3 Aug 2022 01:11:07 +0300
From: Iskren Chernev <iskren.chernev@...il.com>
To: Bjorn Andersson <bjorn.andersson@...aro.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Mark Brown <broonie@...nel.org>
Cc: Andy Gross <agross@...nel.org>,
Konrad Dybcio <konrad.dybcio@...ainline.org>,
Liam Girdwood <lgirdwood@...il.com>,
Rob Herring <robh+dt@...nel.org>,
Robert Marko <robimarko@...il.com>, devicetree@...r.kernel.org,
linux-arm-msm@...r.kernel.org, linux-kernel@...r.kernel.org,
phone-devel@...r.kernel.org, ~postmarketos/upstreaming@...ts.sr.ht,
Iskren Chernev <iskren.chernev@...il.com>
Subject: [PATCH v4 08/13] regulator: qcom_spmi: Sort pmics alphabetically (part 2)
The sorting is split in multiple commits for easier reviewing.
Signed-off-by: Iskren Chernev <iskren.chernev@...il.com>
---
drivers/regulator/qcom_spmi-regulator.c | 129 ++++++++++++------------
1 file changed, 64 insertions(+), 65 deletions(-)
diff --git a/drivers/regulator/qcom_spmi-regulator.c b/drivers/regulator/qcom_spmi-regulator.c
index 4c6494e3bbf6..aed818c7a4d4 100644
--- a/drivers/regulator/qcom_spmi-regulator.c
+++ b/drivers/regulator/qcom_spmi-regulator.c
@@ -2021,6 +2021,68 @@ static int spmi_regulator_of_parse(struct device_node *node,
return 0;
}
+static const struct spmi_regulator_data pm660_regulators[] = {
+ { "s1", 0x1400, "vdd_s1", },
+ { "s2", 0x1700, "vdd_s2", },
+ { "s3", 0x1a00, "vdd_s3", },
+ { "s4", 0x1d00, "vdd_s3", },
+ { "s5", 0x2000, "vdd_s5", },
+ { "s6", 0x2300, "vdd_s6", },
+ { "l1", 0x4000, "vdd_l1_l6_l7", },
+ { "l2", 0x4100, "vdd_l2_l3", },
+ { "l3", 0x4200, "vdd_l2_l3", },
+ /* l4 is unaccessible on PM660 */
+ { "l5", 0x4400, "vdd_l5", },
+ { "l6", 0x4500, "vdd_l1_l6_l7", },
+ { "l7", 0x4600, "vdd_l1_l6_l7", },
+ { "l8", 0x4700, "vdd_l8_l9_l10_l11_l12_l13_l14", },
+ { "l9", 0x4800, "vdd_l8_l9_l10_l11_l12_l13_l14", },
+ { "l10", 0x4900, "vdd_l8_l9_l10_l11_l12_l13_l14", },
+ { "l11", 0x4a00, "vdd_l8_l9_l10_l11_l12_l13_l14", },
+ { "l12", 0x4b00, "vdd_l8_l9_l10_l11_l12_l13_l14", },
+ { "l13", 0x4c00, "vdd_l8_l9_l10_l11_l12_l13_l14", },
+ { "l14", 0x4d00, "vdd_l8_l9_l10_l11_l12_l13_l14", },
+ { "l15", 0x4e00, "vdd_l15_l16_l17_l18_l19", },
+ { "l16", 0x4f00, "vdd_l15_l16_l17_l18_l19", },
+ { "l17", 0x5000, "vdd_l15_l16_l17_l18_l19", },
+ { "l18", 0x5100, "vdd_l15_l16_l17_l18_l19", },
+ { "l19", 0x5200, "vdd_l15_l16_l17_l18_l19", },
+ { }
+};
+
+static const struct spmi_regulator_data pm660l_regulators[] = {
+ { "s1", 0x1400, "vdd_s1", },
+ { "s2", 0x1700, "vdd_s2", },
+ { "s3", 0x1a00, "vdd_s3", },
+ { "s4", 0x1d00, "vdd_s4", },
+ { "s5", 0x2000, "vdd_s5", },
+ { "l1", 0x4000, "vdd_l1_l9_l10", },
+ { "l2", 0x4100, "vdd_l2", },
+ { "l3", 0x4200, "vdd_l3_l5_l7_l8", },
+ { "l4", 0x4300, "vdd_l4_l6", },
+ { "l5", 0x4400, "vdd_l3_l5_l7_l8", },
+ { "l6", 0x4500, "vdd_l4_l6", },
+ { "l7", 0x4600, "vdd_l3_l5_l7_l8", },
+ { "l8", 0x4700, "vdd_l3_l5_l7_l8", },
+ { "l9", 0x4800, "vdd_l1_l9_l10", },
+ { "l10", 0x4900, "vdd_l1_l9_l10", },
+ { }
+};
+
+static const struct spmi_regulator_data pm8004_regulators[] = {
+ { "s2", 0x1700, "vdd_s2", },
+ { "s5", 0x2000, "vdd_s5", },
+ { }
+};
+
+static const struct spmi_regulator_data pm8005_regulators[] = {
+ { "s1", 0x1400, "vdd_s1", },
+ { "s2", 0x1700, "vdd_s2", },
+ { "s3", 0x1a00, "vdd_s3", },
+ { "s4", 0x1d00, "vdd_s4", },
+ { }
+};
+
static const struct spmi_regulator_data pm8226_regulators[] = {
{ "s1", 0x1400, "vdd_s1", },
{ "s2", 0x1700, "vdd_s2", },
@@ -2225,69 +2287,6 @@ static const struct spmi_regulator_data pmi8994_regulators[] = {
{ }
};
-static const struct spmi_regulator_data pm660_regulators[] = {
- { "s1", 0x1400, "vdd_s1", },
- { "s2", 0x1700, "vdd_s2", },
- { "s3", 0x1a00, "vdd_s3", },
- { "s4", 0x1d00, "vdd_s3", },
- { "s5", 0x2000, "vdd_s5", },
- { "s6", 0x2300, "vdd_s6", },
- { "l1", 0x4000, "vdd_l1_l6_l7", },
- { "l2", 0x4100, "vdd_l2_l3", },
- { "l3", 0x4200, "vdd_l2_l3", },
- /* l4 is unaccessible on PM660 */
- { "l5", 0x4400, "vdd_l5", },
- { "l6", 0x4500, "vdd_l1_l6_l7", },
- { "l7", 0x4600, "vdd_l1_l6_l7", },
- { "l8", 0x4700, "vdd_l8_l9_l10_l11_l12_l13_l14", },
- { "l9", 0x4800, "vdd_l8_l9_l10_l11_l12_l13_l14", },
- { "l10", 0x4900, "vdd_l8_l9_l10_l11_l12_l13_l14", },
- { "l11", 0x4a00, "vdd_l8_l9_l10_l11_l12_l13_l14", },
- { "l12", 0x4b00, "vdd_l8_l9_l10_l11_l12_l13_l14", },
- { "l13", 0x4c00, "vdd_l8_l9_l10_l11_l12_l13_l14", },
- { "l14", 0x4d00, "vdd_l8_l9_l10_l11_l12_l13_l14", },
- { "l15", 0x4e00, "vdd_l15_l16_l17_l18_l19", },
- { "l16", 0x4f00, "vdd_l15_l16_l17_l18_l19", },
- { "l17", 0x5000, "vdd_l15_l16_l17_l18_l19", },
- { "l18", 0x5100, "vdd_l15_l16_l17_l18_l19", },
- { "l19", 0x5200, "vdd_l15_l16_l17_l18_l19", },
- { }
-};
-
-static const struct spmi_regulator_data pm660l_regulators[] = {
- { "s1", 0x1400, "vdd_s1", },
- { "s2", 0x1700, "vdd_s2", },
- { "s3", 0x1a00, "vdd_s3", },
- { "s4", 0x1d00, "vdd_s4", },
- { "s5", 0x2000, "vdd_s5", },
- { "l1", 0x4000, "vdd_l1_l9_l10", },
- { "l2", 0x4100, "vdd_l2", },
- { "l3", 0x4200, "vdd_l3_l5_l7_l8", },
- { "l4", 0x4300, "vdd_l4_l6", },
- { "l5", 0x4400, "vdd_l3_l5_l7_l8", },
- { "l6", 0x4500, "vdd_l4_l6", },
- { "l7", 0x4600, "vdd_l3_l5_l7_l8", },
- { "l8", 0x4700, "vdd_l3_l5_l7_l8", },
- { "l9", 0x4800, "vdd_l1_l9_l10", },
- { "l10", 0x4900, "vdd_l1_l9_l10", },
- { }
-};
-
-
-static const struct spmi_regulator_data pm8004_regulators[] = {
- { "s2", 0x1700, "vdd_s2", },
- { "s5", 0x2000, "vdd_s5", },
- { }
-};
-
-static const struct spmi_regulator_data pm8005_regulators[] = {
- { "s1", 0x1400, "vdd_s1", },
- { "s2", 0x1700, "vdd_s2", },
- { "s3", 0x1a00, "vdd_s3", },
- { "s4", 0x1d00, "vdd_s4", },
- { }
-};
-
static const struct spmi_regulator_data pmp8074_regulators[] = {
{ "s1", 0x1400, "vdd_s1"},
{ "s2", 0x1700, "vdd_s2"},
@@ -2316,6 +2315,8 @@ static const struct spmi_regulator_data pms405_regulators[] = {
};
static const struct of_device_id qcom_spmi_regulator_match[] = {
+ { .compatible = "qcom,pm660-regulators", .data = &pm660_regulators },
+ { .compatible = "qcom,pm660l-regulators", .data = &pm660l_regulators },
{ .compatible = "qcom,pm8004-regulators", .data = &pm8004_regulators },
{ .compatible = "qcom,pm8005-regulators", .data = &pm8005_regulators },
{ .compatible = "qcom,pm8226-regulators", .data = &pm8226_regulators },
@@ -2325,8 +2326,6 @@ static const struct of_device_id qcom_spmi_regulator_match[] = {
{ .compatible = "qcom,pm8950-regulators", .data = &pm8950_regulators },
{ .compatible = "qcom,pm8994-regulators", .data = &pm8994_regulators },
{ .compatible = "qcom,pmi8994-regulators", .data = &pmi8994_regulators },
- { .compatible = "qcom,pm660-regulators", .data = &pm660_regulators },
- { .compatible = "qcom,pm660l-regulators", .data = &pm660l_regulators },
{ .compatible = "qcom,pmp8074-regulators", .data = &pmp8074_regulators },
{ .compatible = "qcom,pms405-regulators", .data = &pms405_regulators },
{ }
--
2.37.1
Powered by blists - more mailing lists