linux-kernel - Re: [PATCH] x86/fpu: Allow PKRU to be (once again) written by ptrace.

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Message-ID: <Yuqvkufu7Hu4drL6@gmail.com>
Date:   Wed, 3 Aug 2022 19:25:38 +0200
From:   Ingo Molnar <mingo@...nel.org>
To:     Kyle Huey <me@...ehuey.com>
Cc:     Dave Hansen <dave.hansen@...ux.intel.com>,
        Thomas Gleixner <tglx@...utronix.de>,
        Borislav Petkov <bp@...en8.de>, Ingo Molnar <mingo@...hat.com>,
        x86@...nel.org, "H. Peter Anvin" <hpa@...or.com>,
        Paolo Bonzini <pbonzini@...hat.com>,
        Andy Lutomirski <luto@...nel.org>,
        Peter Zijlstra <peterz@...radead.org>,
        linux-kernel@...r.kernel.org,
        Robert O'Callahan <robert@...llahan.org>,
        David Manouchehri <david.manouchehri@...eup.net>,
        kvm@...r.kernel.org, stable@...r.kernel.org
Subject: Re: [PATCH] x86/fpu: Allow PKRU to be (once again) written by ptrace.


* Kyle Huey <me@...ehuey.com> wrote:

> > Also, what's the security model for this register, do we trust all 
> > input values user-space provides for the PKRU field in the XSTATE? I 
> > realize that WRPKRU already gives user-space write access to the 
> > register - but does the CPU write it all into the XSTATE, with no 
> > restrictions on content whatsoever?
> 
> There is no security model for this register. The CPU does write whatever 
> is given to WRPKRU (or XRSTOR) into the PKRU register. The pkeys(7) man 
> page notes:
> 
> Protection keys have the potential to add a layer of security and 
> reliability to applications. But they have not been primarily designed as 
> a security feature. For instance, WRPKRU is a completely unprivileged 
> instruction, so pkeys are useless in any case that an attacker controls 
> the PKRU register or can execute arbitrary instructions.

Ok - allowing ptrace to set the full 32 bits of the PKRU register seems OK 
then, and is 100% equivalent to using WRPKRU, right? So there's no implicit 
masking/clearing of bits depending on how many keys are available, or other 
details where WRPKRU might differ from a pure 32-bit per thread write, 
correct?

Thanks,

	Ingo