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Message-ID: <f54deddd-251d-aa8c-6946-f447077d7782@linaro.org>
Date: Thu, 4 Aug 2022 17:22:50 +0200
From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To: bchihi@...libre.com, rafael@...nel.org, rui.zhang@...el.com,
daniel.lezcano@...aro.org, amitk@...nel.org
Cc: linux-pm@...r.kernel.org, linux-kernel@...r.kernel.org,
khilman@...libre.com, mka@...omium.org, robh+dt@...nel.org,
krzk+dt@...nel.org, matthias.bgg@...il.com, p.zabel@...gutronix.de,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org, james.lo@...iatek.com,
fan.chen@...iatek.com, louis.yu@...iatek.com,
rex-bc.chen@...iatek.com, abailon@...libre.com
Subject: Re: [PATCH v8.1, 6/7] arm64: dts: mt8195: Add thermal zone
On 04/08/2022 15:09, bchihi@...libre.com wrote:
> From: Tinghan Shen <tinghan.shen@...iatek.com>
>
> This adds the thermal zone for the mt8195.
>
> Signed-off-by: Tinghan Shen <tinghan.shen@...iatek.com>
> Signed-off-by: Ben Tseng <ben.tseng@...iatek.com>
> Signed-off-by: Alexandre Bailon <abailon@...libre.com>
> Signed-off-by: Balsam CHIHI <bchihi@...libre.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8195.dtsi | 111 +++++++++++++++++++++++
> 1 file changed, 111 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> index cbd0401968a2..5890e688eebe 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> @@ -10,6 +10,7 @@
> #include <dt-bindings/interrupt-controller/irq.h>
> #include <dt-bindings/phy/phy.h>
> #include <dt-bindings/pinctrl/mt8195-pinfunc.h>
> +#include <dt-bindings/reset/mt8195-resets.h>
>
> / {
> compatible = "mediatek,mt8195";
> @@ -452,6 +453,28 @@ spi0: spi@...0a000 {
> status = "disabled";
> };
>
> + lvts_ap: thermal-sensor@...0b000 {
> + compatible = "mediatek,mt8195-lvts-ap";
> + #thermal-sensor-cells = <1>;
> + reg = <0 0x1100b000 0 0x1000>;
> + interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&infracfg_ao CLK_INFRA_AO_THERM>;
> + resets = <&infracfg_ao MT8195_INFRA_RST0_THERM_CTRL_SWRST>;
> + nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>;
> + nvmem-cell-names = "lvts_calib_data1", "lvts_calib_data2";
> + };
> +
> + lvts_mcu: thermal-sensor@...78000 {
> + compatible = "mediatek,mt8195-lvts-mcu";
> + #thermal-sensor-cells = <1>;
> + reg = <0 0x11278000 0 0x1000>;
> + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&infracfg_ao CLK_INFRA_AO_THERM>;
> + resets = <&infracfg_ao MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST>;
> + nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>;
> + nvmem-cell-names = "lvts_calib_data1", "lvts_calib_data2";
> + };
> +
> spi1: spi@...10000 {
> compatible = "mediatek,mt8195-spi",
> "mediatek,mt6765-spi";
> @@ -1106,4 +1129,92 @@ vencsys_core1: clock-controller@...00000 {
> #clock-cells = <1>;
> };
> };
> +
> + thermal_zones: thermal-zones {
> + cpu-big1-thermal {
Does this pass dtbs_check?
Best regards,
Krzysztof
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