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Message-ID: <20220804021553.14867-17-tinghan.shen@mediatek.com>
Date: Thu, 4 Aug 2022 10:15:49 +0800
From: Tinghan Shen <tinghan.shen@...iatek.com>
To: Yong Wu <yong.wu@...iatek.com>, Joerg Roedel <joro@...tes.org>,
Will Deacon <will@...nel.org>,
Robin Murphy <robin.murphy@....com>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Lee Jones <lee@...nel.org>,
Matthias Brugger <matthias.bgg@...il.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>,
Tinghan Shen <tinghan.shen@...iatek.com>,
MandyJH Liu <mandyjh.liu@...iatek.com>
CC: <iommu@...ts.linux.dev>, <linux-mediatek@...ts.infradead.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<Project_Global_Chrome_Upstream_Group@...iatek.com>,
YC Hung <yc.hung@...iatek.corp-partner.google.com>,
Allen-KH Cheng <allen-kh.cheng@...iatek.corp-partner.google.com>
Subject: [PATCH v5 16/20] arm64: dts: mt8195: Add adsp node and adsp mailbox nodes
From: YC Hung <yc.hung@...iatek.corp-partner.google.com>
Add adsp node and adsp mailbox nodes for mt8195.
Signed-off-by: YC Hung <yc.hung@...iatek.corp-partner.google.com>
Signed-off-by: Allen-KH Cheng
<allen-kh.cheng@...iatek.corp-partner.google.com>
Signed-off-by: Tinghan Shen <tinghan.shen@...iatek.com>
Reviewed-by: AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 37 ++++++++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index bbea0acff3d2f..f42d33414125f 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -739,6 +739,43 @@
#clock-cells = <1>;
};
+ adsp: dsp@...03000 {
+ compatible = "mediatek,mt8195-dsp";
+ reg = <0 0x10803000 0 0x1000>,
+ <0 0x10840000 0 0x40000>;
+ reg-names = "cfg", "sram";
+ clocks = <&topckgen CLK_TOP_ADSP>,
+ <&clk26m>,
+ <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>,
+ <&topckgen CLK_TOP_MAINPLL_D7_D2>,
+ <&scp_adsp CLK_SCP_ADSP_AUDIODSP>,
+ <&topckgen CLK_TOP_AUDIO_H>;
+ clock-names = "adsp_sel",
+ "clk26m_ck",
+ "audio_local_bus",
+ "mainpll_d7_d2",
+ "scp_adsp_audiodsp",
+ "audio_h";
+ power-domains = <&spm MT8195_POWER_DOMAIN_ADSP>;
+ mbox-names = "rx", "tx";
+ mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>;
+ status = "disabled";
+ };
+
+ adsp_mailbox0: mailbox@...16000 {
+ compatible = "mediatek,mt8195-adsp-mbox";
+ #mbox-cells = <0>;
+ reg = <0 0x10816000 0 0x1000>;
+ interrupts = <GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH 0>;
+ };
+
+ adsp_mailbox1: mailbox@...17000 {
+ compatible = "mediatek,mt8195-adsp-mbox";
+ #mbox-cells = <0>;
+ reg = <0 0x10817000 0 0x1000>;
+ interrupts = <GIC_SPI 703 IRQ_TYPE_LEVEL_HIGH 0>;
+ };
+
afe: mt8195-afe-pcm@...90000 {
compatible = "mediatek,mt8195-audio";
reg = <0 0x10890000 0 0x10000>;
--
2.18.0
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