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Message-ID: <20220805053019.996484-2-nagasuresh.relli@microchip.com>
Date: Fri, 5 Aug 2022 11:00:16 +0530
From: Naga Sureshkumar Relli <nagasuresh.relli@...rochip.com>
To: <broonie@...nel.org>, <robh+dt@...nel.org>,
<krzysztof.kozlowski+dt@...aro.org>, <conor.dooley@...rochip.com>
CC: <linux-spi@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>,
<Valentina.FernandezAlanis@...rochip.com>,
Naga Sureshkumar Relli <nagasuresh.relli@...rochip.com>
Subject: [PATCH v3 1/4] spi: dt-binding: document microchip coreQSPI
Add microchip coreQSPI compatible string and update the title/description
to reflect this addition.
Signed-off-by: Naga Sureshkumar Relli <nagasuresh.relli@...rochip.com>
---
.../devicetree/bindings/spi/microchip,mpfs-spi.yaml | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml b/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
index 7326c0a28d16..a47d4923b51b 100644
--- a/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
+++ b/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
@@ -4,7 +4,11 @@
$id: http://devicetree.org/schemas/spi/microchip,mpfs-spi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Microchip MPFS {Q,}SPI Controller Device Tree Bindings
+title: Microchip FPGA {Q,}SPI Controllers
+
+description:
+ SPI and QSPI controllers on Microchip PolarFire SoC and the "soft"/
+ fabric IP cores they are based on
maintainers:
- Conor Dooley <conor.dooley@...rochip.com>
@@ -17,6 +21,7 @@ properties:
enum:
- microchip,mpfs-spi
- microchip,mpfs-qspi
+ - microchip,coreqspi-rtl-v2 # FPGA QSPI
reg:
maxItems: 1
--
2.25.1
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