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Message-ID: <20220805053019.996484-3-nagasuresh.relli@microchip.com>
Date:   Fri, 5 Aug 2022 11:00:17 +0530
From:   Naga Sureshkumar Relli <nagasuresh.relli@...rochip.com>
To:     <broonie@...nel.org>, <robh+dt@...nel.org>,
        <krzysztof.kozlowski+dt@...aro.org>, <conor.dooley@...rochip.com>
CC:     <linux-spi@...r.kernel.org>, <devicetree@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>,
        <Valentina.FernandezAlanis@...rochip.com>,
        Naga Sureshkumar Relli <nagasuresh.relli@...rochip.com>
Subject: [PATCH v3 2/4] spi: dt-binding: add coreqspi as a fallback for mpfs-qspi

Microchip's PolarFire SoC QSPI IP core is based on coreQSPI,
so add coreqspi as a fallback to mpfs-qspi.

Signed-off-by: Naga Sureshkumar Relli <nagasuresh.relli@...rochip.com>
---
 .../devicetree/bindings/spi/microchip,mpfs-spi.yaml    | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml b/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
index a47d4923b51b..84d32c1a4d60 100644
--- a/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
+++ b/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
@@ -18,10 +18,12 @@ allOf:
 
 properties:
   compatible:
-    enum:
-      - microchip,mpfs-spi
-      - microchip,mpfs-qspi
-      - microchip,coreqspi-rtl-v2 # FPGA QSPI
+   oneOf:
+    - items:
+        - const: microchip,mpfs-qspi
+        - const: microchip,coreqspi-rtl-v2
+    - const: microchip,coreqspi-rtl-v2 #FPGA QSPI
+    - const: microchip,mpfs-spi
 
   reg:
     maxItems: 1
-- 
2.25.1

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