[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <76efe86bb6ffa2447fd68ea9f77d86712bf44662.camel@mediatek.com>
Date: Tue, 9 Aug 2022 16:01:33 +0800
From: Bo-Chen Chen <rex-bc.chen@...iatek.com>
To: CK Hu <ck.hu@...iatek.com>,
"chunkuang.hu@...nel.org" <chunkuang.hu@...nel.org>,
"p.zabel@...gutronix.de" <p.zabel@...gutronix.de>,
"daniel@...ll.ch" <daniel@...ll.ch>,
"robh+dt@...nel.org" <robh+dt@...nel.org>,
"krzysztof.kozlowski+dt@...aro.org"
<krzysztof.kozlowski+dt@...aro.org>,
"mripard@...nel.org" <mripard@...nel.org>,
"tzimmermann@...e.de" <tzimmermann@...e.de>,
"matthias.bgg@...il.com" <matthias.bgg@...il.com>,
"deller@....de" <deller@....de>,
"airlied@...ux.ie" <airlied@...ux.ie>
CC: "msp@...libre.com" <msp@...libre.com>,
"granquet@...libre.com" <granquet@...libre.com>,
Jitao Shi (石记涛)
<jitao.shi@...iatek.com>,
"wenst@...omium.org" <wenst@...omium.org>,
"angelogioacchino.delregno@...labora.com"
<angelogioacchino.delregno@...labora.com>,
LiangXu Xu (徐亮)
<LiangXu.Xu@...iatek.com>,
"dri-devel@...ts.freedesktop.org" <dri-devel@...ts.freedesktop.org>,
"linux-mediatek@...ts.infradead.org"
<linux-mediatek@...ts.infradead.org>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"linux-fbdev@...r.kernel.org" <linux-fbdev@...r.kernel.org>,
Project_Global_Chrome_Upstream_Group
<Project_Global_Chrome_Upstream_Group@...iatek.com>
Subject: Re: [PATCH v16 3/8] drm/mediatek: Add MT8195 Embedded DisplayPort
driver
On Mon, 2022-08-08 at 16:04 +0800, CK Hu wrote:
> Hi, Bo-Chen:
>
> On Fri, 2022-08-05 at 18:14 +0800, Bo-Chen Chen wrote:
> > From: Markus Schneider-Pargmann <msp@...libre.com>
> >
> > This patch adds a embedded displayport driver for the MediaTek
> > mt8195
> > SoC.
> >
> > It supports the MT8195, the embedded DisplayPort units. It offers
> > DisplayPort 1.4 with up to 4 lanes.
> >
> > The driver creates a child device for the phy. The child device
> > will
> > never exist without the parent being active. As they are sharing a
> > register range, the parent passes a regmap pointer to the child so
> > that
> > both can work with the same register range. The phy driver sets
> > device
> > data that is read by the parent to get the phy device that can be
> > used
> > to control the phy properties.
> >
> > This driver is based on an initial version by
> > Jitao shi <jitao.shi@...iatek.com>
> >
> > Signed-off-by: Markus Schneider-Pargmann <msp@...libre.com>
> > Signed-off-by: Guillaume Ranquet <granquet@...libre.com>
> > Signed-off-by: Bo-Chen Chen <rex-bc.chen@...iatek.com>
> > Tested-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno@...labora.com>
> > Reviewed-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno@...labora.com>
> > ---
>
> [snip]
>
> > +
> > +static enum drm_mode_status
> > +mtk_dp_bridge_mode_valid(struct drm_bridge *bridge,
> > + const struct drm_display_info *info,
> > + const struct drm_display_mode *mode)
> > +{
> > + struct mtk_dp *mtk_dp = mtk_dp_from_bridge(bridge);
> > + u32 rx_linkrate = (u32)mtk_dp->train_info.link_rate * 27000;
> > + u32 bpp = info->color_formats & DRM_COLOR_FORMAT_YCBCR422 ? 16
> > : 24;
> > +
> > + if (rx_linkrate * mtk_dp->train_info.lane_count < mode->clock *
> > bpp / 8)
> > + return MODE_CLOCK_HIGH;
> > +
> > + if (mode->clock > 600000)
>
> If the clock has pass the linkrate and land_count limitation, the
> clock
> would be OK because the linkrate and lane_count is trained. Why need
> to
> check 600000?
>
> Regards,
> CK
>
Hello CK,
The condition above is enough to cover this.
I will drop this check.
BRs,
Bo-Chen
> > + return MODE_CLOCK_HIGH;
> > +
> > + return MODE_OK;
> > +}
> > +
>
>
Powered by blists - more mailing lists