lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <13df168d-e414-e167-c3c9-c04eb29c675a@microchip.com>
Date:   Tue, 9 Aug 2022 17:30:23 +0000
From:   <Conor.Dooley@...rochip.com>
To:     <robh@...nel.org>
CC:     <tglx@...utronix.de>, <maz@...nel.org>,
        <krzysztof.kozlowski+dt@...aro.org>, <mail@...chuod.ie>,
        <palmer@...belt.com>, <paul.walmsley@...ive.com>,
        <aou@...s.berkeley.edu>, <daniel.lezcano@...aro.org>,
        <anup@...infault.org>, <guoren@...nel.org>,
        <sagar.kadam@...ive.com>, <linux-kernel@...r.kernel.org>,
        <devicetree@...r.kernel.org>, <linux-riscv@...ts.infradead.org>,
        <qemu-riscv@...gnu.org>
Subject: Re: [PATCH 1/3] dt-bindings: timer: sifive,clint: add legacy riscv
 compatible

On 09/08/2022 15:16, Rob Herring wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> On Fri, Aug 05, 2022 at 05:28:43PM +0100, Conor Dooley wrote:
>> From: Conor Dooley <conor.dooley@...rochip.com>
>>
>> While "real" hardware might not use the compatible string "riscv,clint0"
>> it is present in the driver & QEMU uses it for automatically generated
>> virt machine dtbs. To avoid dt-validate problems with QEMU produced
>> dtbs, such as the following, add it to the binding.
>>
>> riscv-virt.dtb: clint@...0000: compatible:0: 'sifive,clint0' is not one of ['sifive,fu540-c000-clint', 'starfive,jh7100-clint', 'canaan,k210-clint']
>>
>> Reported-by: Rob Herring <robh@...nel.org>
>> Link: https://lore.kernel.org/linux-riscv/20220803170552.GA2250266-robh@kernel.org/
>> Signed-off-by: Conor Dooley <conor.dooley@...rochip.com>
>> ---
>>  .../bindings/timer/sifive,clint.yaml           | 18 ++++++++++++------
>>  1 file changed, 12 insertions(+), 6 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
>> index e64f46339079..9fcf20942582 100644
>> --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
>> +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
>> @@ -22,12 +22,18 @@ description:
>>
>>  properties:
>>    compatible:
>> -    items:
>> -      - enum:
>> -          - sifive,fu540-c000-clint
>> -          - starfive,jh7100-clint
>> -          - canaan,k210-clint
>> -      - const: sifive,clint0
>> +    oneOf:
>> +      - items:
>> +          - enum:
>> +              - sifive,fu540-c000-clint
>> +              - starfive,jh7100-clint
>> +              - canaan,k210-clint
>> +          - const: sifive,clint0
>> +      - items:
>> +          - const: sifive,clint0
>> +          - const: riscv,clint0
>> +        deprecated: true
>> +        description: For legacy systems & the qemu virt machine only
> 
> I would drop 'legacy systems'.

I took this from a comment in the driver against "riscv,plic0". Thought
it applied to both plic and clint bindings so put it in here. Happy to
drop them for v2 :)

Thanks,
Conor.

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ