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Message-ID: <87o7wsbngz.wl-maz@kernel.org>
Date: Wed, 10 Aug 2022 07:51:24 +0100
From: Marc Zyngier <maz@...nel.org>
To: Dmytro Maluka <dmy@...ihalf.com>
Cc: "Dong, Eddie" <eddie.dong@...el.com>,
"Christopherson,, Sean" <seanjc@...gle.com>,
Paolo Bonzini <pbonzini@...hat.com>,
"kvm@...r.kernel.org" <kvm@...r.kernel.org>,
Thomas Gleixner <tglx@...utronix.de>,
Ingo Molnar <mingo@...hat.com>, Borislav Petkov <bp@...en8.de>,
Dave Hansen <dave.hansen@...ux.intel.com>,
"x86@...nel.org" <x86@...nel.org>,
"H. Peter Anvin" <hpa@...or.com>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
Eric Auger <eric.auger@...hat.com>,
Alex Williamson <alex.williamson@...hat.com>,
"Liu, Rong L" <rong.l.liu@...el.com>,
Zhenyu Wang <zhenyuw@...ux.intel.com>,
Tomasz Nowicki <tn@...ihalf.com>,
Grzegorz Jaszczyk <jaz@...ihalf.com>,
"upstream@...ihalf.com" <upstream@...ihalf.com>,
Dmitry Torokhov <dtor@...gle.com>
Subject: Re: [PATCH v2 0/5] KVM: Fix oneshot interrupts forwarding
On Wed, 10 Aug 2022 00:30:29 +0100,
Dmytro Maluka <dmy@...ihalf.com> wrote:
>
> On 8/9/22 10:01 PM, Dong, Eddie wrote:
> >
> >
> >> -----Original Message-----
> >> From: Dmytro Maluka <dmy@...ihalf.com>
> >> Sent: Tuesday, August 9, 2022 12:24 AM
> >> To: Dong, Eddie <eddie.dong@...el.com>; Christopherson,, Sean
> >> <seanjc@...gle.com>; Paolo Bonzini <pbonzini@...hat.com>;
> >> kvm@...r.kernel.org
> >> Cc: Thomas Gleixner <tglx@...utronix.de>; Ingo Molnar <mingo@...hat.com>;
> >> Borislav Petkov <bp@...en8.de>; Dave Hansen <dave.hansen@...ux.intel.com>;
> >> x86@...nel.org; H. Peter Anvin <hpa@...or.com>; linux-
> >> kernel@...r.kernel.org; Eric Auger <eric.auger@...hat.com>; Alex
> >> Williamson <alex.williamson@...hat.com>; Liu, Rong L <rong.l.liu@...el.com>;
> >> Zhenyu Wang <zhenyuw@...ux.intel.com>; Tomasz Nowicki
> >> <tn@...ihalf.com>; Grzegorz Jaszczyk <jaz@...ihalf.com>;
> >> upstream@...ihalf.com; Dmitry Torokhov <dtor@...gle.com>
> >> Subject: Re: [PATCH v2 0/5] KVM: Fix oneshot interrupts forwarding
> >>
> >> On 8/9/22 1:26 AM, Dong, Eddie wrote:
> >>>>
> >>>> The existing KVM mechanism for forwarding of level-triggered
> >>>> interrupts using resample eventfd doesn't work quite correctly in the
> >>>> case of interrupts that are handled in a Linux guest as oneshot
> >>>> interrupts (IRQF_ONESHOT). Such an interrupt is acked to the device
> >>>> in its threaded irq handler, i.e. later than it is acked to the
> >>>> interrupt controller (EOI at the end of hardirq), not earlier. The
> >>>> existing KVM code doesn't take that into account, which results in
> >>>> erroneous extra interrupts in the guest caused by premature re-assert of an
> >> unacknowledged IRQ by the host.
> >>>
> >>> Interesting... How it behaviors in native side?
> >>
> >> In native it behaves correctly, since Linux masks such a oneshot interrupt at the
> >> beginning of hardirq, so that the EOI at the end of hardirq doesn't result in its
> >> immediate re-assert, and then unmasks it later, after its threaded irq handler
> >> completes.
> >>
> >> In handle_fasteoi_irq():
> >>
> >> if (desc->istate & IRQS_ONESHOT)
> >> mask_irq(desc);
> >>
> >> handle_irq_event(desc);
> >>
> >> cond_unmask_eoi_irq(desc, chip);
> >>
> >>
> >> and later in unmask_threaded_irq():
> >>
> >> unmask_irq(desc);
> >>
> >> I also mentioned that in patch #3 description:
> >> "Linux keeps such interrupt masked until its threaded handler finishes, to
> >> prevent the EOI from re-asserting an unacknowledged interrupt.
> >
> > That makes sense. Can you include the full story in cover letter too?
>
> Ok, I will.
>
> >
> >
> >> However, with KVM + vfio (or whatever is listening on the resamplefd) we don't
> >> check that the interrupt is still masked in the guest at the moment of EOI.
> >> Resamplefd is notified regardless, so vfio prematurely unmasks the host
> >> physical IRQ, thus a new (unwanted) physical interrupt is generated in the host
> >> and queued for injection to the guest."
Sorry to barge in pretty late in the conversation (just been Cc'd on
this), but why shouldn't the resamplefd be notified? If there has been
an EOI, a new level must be made visible to the guest interrupt
controller, no matter what the state of the interrupt masking is.
Whether this new level is actually *presented* to a vCPU is another
matter entirely, and is arguably a problem for the interrupt
controller emulation.
For example on arm64, we expect to be able to read the pending state
of an interrupt from the guest irrespective of the masking state of
that interrupt. Any change to the interrupt flow should preserve this.
Thankfully, we don't have the polarity issue (there is no such thing
in the GIC architecture) and we only deal with pending/not-pending.
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
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