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Date: Thu, 11 Aug 2022 14:06:56 -0700 (PDT) From: Palmer Dabbelt <palmer@...belt.com> To: kettenis@...nbsd.org CC: mail@...chuod.ie, robh+dt@...nel.org, krzysztof.kozlowski+dt@...aro.org, Paul Walmsley <paul.walmsley@...ive.com>, aou@...s.berkeley.edu, kernel@...il.dk, kettenis@...nbsd.org, devicetree@...r.kernel.org, linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org Subject: Re: [PATCH v2] riscv: dts: starfive: correct number of external interrupts On Thu, 07 Jul 2022 11:55:28 PDT (-0700), kettenis@...nbsd.org wrote: > The PLIC integrated on the Vic_U7_Core integrated on the StarFive > JH7100 SoC actually supports 133 external interrupts. 127 of these > are exposed to the outside world; the remainder are used by other > devices that are part of the core-complex such as the L2 cache > controller. But all 133 interrupts are external interrupts as far > as the PLIC is concerned. Fix the property so that the driver can > manage these additional interrupts, which is important since the > interrupts for the L2 cache controller are enabled by default. > > Fixes: ec85362fb121 ("RISC-V: Add initial StarFive JH7100 device tree") > Signed-off-by: Mark Kettenis <kettenis@...nbsd.org> > --- > > ChangeLog: > > v2: - Fix commit message > > > arch/riscv/boot/dts/starfive/jh7100.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi > index 69f22f9aad9d..f48e232a72a7 100644 > --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi > +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi > @@ -118,7 +118,7 @@ plic: interrupt-controller@...0000 { > interrupt-controller; > #address-cells = <0>; > #interrupt-cells = <1>; > - riscv,ndev = <127>; > + riscv,ndev = <133>; > }; > > clkgen: clock-controller@...00000 { Thanks, this is on for-next.
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