lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Fri, 12 Aug 2022 10:33:06 +0200
From:   Jiri Olsa <olsajiri@...il.com>
To:     Sandipan Das <sandipan.das@....com>
Cc:     linux-kernel@...r.kernel.org, linux-perf-users@...r.kernel.org,
        x86@...nel.org, peterz@...radead.org, bp@...en8.de,
        acme@...nel.org, namhyung@...nel.org, tglx@...utronix.de,
        mingo@...hat.com, mark.rutland@....com,
        alexander.shishkin@...ux.intel.com, dave.hansen@...ux.intel.com,
        like.xu.linux@...il.com, eranian@...gle.com,
        ananth.narayan@....com, ravi.bangoria@....com,
        santosh.shukla@....com
Subject: Re: [PATCH 2/4] tools headers x86: Sync msr-index.h with kernel
 sources

On Thu, Aug 11, 2022 at 06:16:47PM +0530, Sandipan Das wrote:
> Sync msr-index.h with the kernel sources by adding the new AMD Last Branch
> Record Extension Version 2 (LbrExtV2) MSRs.
> 
> Signed-off-by: Sandipan Das <sandipan.das@....com>
> ---
>  tools/arch/x86/include/asm/msr-index.h | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/tools/arch/x86/include/asm/msr-index.h b/tools/arch/x86/include/asm/msr-index.h
> index cc615be27a54..7f9eaf497947 100644
> --- a/tools/arch/x86/include/asm/msr-index.h
> +++ b/tools/arch/x86/include/asm/msr-index.h
> @@ -574,6 +574,9 @@
>  #define MSR_AMD64_PERF_CNTR_GLOBAL_CTL		0xc0000301
>  #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR	0xc0000302
>  
> +/* AMD Last Branch Record MSRs */
> +#define MSR_AMD64_LBR_SELECT			0xc000010e

curious do we actualy use this in tools somewhere?

jirka

> +
>  /* Fam 17h MSRs */
>  #define MSR_F17H_IRPERF			0xc00000e9
>  
> @@ -745,6 +748,8 @@
>  #define MSR_AMD_DBG_EXTN_CFG		0xc000010f
>  #define MSR_AMD_SAMP_BR_FROM		0xc0010300
>  
> +#define DBG_EXTN_CFG_LBRV2EN		BIT_ULL(6)
> +
>  #define MSR_IA32_MPERF			0x000000e7
>  #define MSR_IA32_APERF			0x000000e8
>  
> -- 
> 2.34.1
> 

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ