[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <bc3d827b-5044-6c8e-6a5a-b0eb679434bb@microchip.com>
Date: Mon, 15 Aug 2022 19:11:44 +0000
From: <Conor.Dooley@...rochip.com>
To: <prabhakar.mahadev-lad.rj@...renesas.com>, <robh+dt@...nel.org>,
<krzysztof.kozlowski+dt@...aro.org>, <paul.walmsley@...ive.com>,
<palmer@...belt.com>, <aou@...s.berkeley.edu>,
<geert+renesas@...der.be>
CC: <anup@...infault.org>, <linux-renesas-soc@...r.kernel.org>,
<devicetree@...r.kernel.org>, <linux-riscv@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>, <prabhakar.csengg@...il.com>,
<biju.das.jz@...renesas.com>
Subject: Re: [PATCH v2 1/8] dt-bindings: riscv: Sort the CPU core list
alphabetically
On 15/08/2022 16:14, Lad Prabhakar wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> Sort the CPU cores list alphabetically for maintenance.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
Speaking of OCD, I like this sort of cleanup 😍
Reviewed-by: Conor Dooley <conor.dooley@...rochip.com>
> ---
> v1->v2
> * Included RB tag from Krzysztof
> ---
> Documentation/devicetree/bindings/riscv/cpus.yaml | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> index 873dd12f6e89..2a1c5ae5b0aa 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> @@ -27,17 +27,17 @@ properties:
> oneOf:
> - items:
> - enum:
> - - sifive,rocket0
> + - canaan,k210
> - sifive,bullet0
> - sifive,e5
> - sifive,e7
> - sifive,e71
> - - sifive,u74-mc
> - - sifive,u54
> - - sifive,u74
> + - sifive,rocket0
> - sifive,u5
> + - sifive,u54
> - sifive,u7
> - - canaan,k210
> + - sifive,u74
> + - sifive,u74-mc
> - const: riscv
> - items:
> - enum:
> --
> 2.25.1
>
Powered by blists - more mailing lists