linux-kernel - Re: [PATCH 7/7] perf/x86/intel/P4: Fix smp_num

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Date:   Tue, 16 Aug 2022 10:26:19 +0800
From:   Zhang Rui <rui.zhang@...el.com>
To:     Peter Zijlstra <peterz@...radead.org>
Cc:     linux-kernel@...r.kernel.org, x86@...nel.org,
        linux-hwmon@...r.kernel.org, tglx@...utronix.de, mingo@...hat.com,
        bp@...en8.de, dave.hansen@...ux.intel.com, hpa@...or.com,
        corbet@....net, fenghua.yu@...el.com, jdelvare@...e.com,
        linux@...ck-us.net, len.brown@...el.com
Subject: Re: [PATCH 7/7] perf/x86/intel/P4: Fix smp_num_siblings usage

On Mon, 2022-08-15 at 11:11 +0200, Peter Zijlstra wrote:
> On Sat, Aug 13, 2022 at 12:41:44AM +0800, Zhang Rui wrote:
> > smp_num_siblings can be larger than 2.
> 
> Not on a P4 it can't ;-)

Kernel code doesn't prevent this from happening, so it just depends on
how SMT ID is encoded in APICID.
Checking for smp_num_sibling > 1 is the right logic to detect HT
support, which is followed by all other kernel code except this one. :)

thanks,
rui
> 
> > Any value larger than 1 suggests HT is supported.
> > 
> > Reviewed-by: Len Brown <len.brown@...el.com>
> > Signed-off-by: Zhang Rui <rui.zhang@...el.com>
> > ---
> >  arch/x86/include/asm/perf_event_p4.h | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/arch/x86/include/asm/perf_event_p4.h
> > b/arch/x86/include/asm/perf_event_p4.h
> > index 94de1a05aeba..b14e9a20a7c0 100644
> > --- a/arch/x86/include/asm/perf_event_p4.h
> > +++ b/arch/x86/include/asm/perf_event_p4.h
> > @@ -189,7 +189,7 @@ static inline int p4_ht_active(void)
> >  static inline int p4_ht_thread(int cpu)
> >  {
> >  #ifdef CONFIG_SMP
> > -	if (smp_num_siblings == 2)
> > +	if (smp_num_siblings > 1)
> >  		return cpu !=
> > cpumask_first(this_cpu_cpumask_var_ptr(cpu_sibling_map));
> >  #endif
> >  	return 0;
> 
> Unless Intel plans to respin an P4 with extra siblings on, I don't
> think
> this qualifies for the word 'fix'.