linux-kernel - [PATCH v2 0/4] Making microcode loading more robust

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Message-Id: <20220816043754.3258815-1-ashok.raj@intel.com>
Date:   Tue, 16 Aug 2022 04:37:49 +0000
From:   Ashok Raj <ashok.raj@...el.com>
To:     Borislav Petkov <bp@...en8.de>,
        Thomas Gleixner <tglx@...utronix.de>
Cc:     "LKML Mailing List" <linux-kernel@...r.kernel.org>,
        Andy Lutomirski <luto@...capital.net>,
        Andrew Cooper <Andrew.Cooper3@...rix.com>,
        "Ashok Raj" <ashok.raj@...el.com>,
        Dave Hansen <dave.hansen@...el.com>,
        Tony Luck <tony.luck@...el.com>
Subject: [PATCH v2 0/4] Making microcode loading more robust

Hi Boris,

Here is an update that handles siblings in NMI loop.

Changes since v1:
Patch 1,2,3: No Change.
Patch 4: 
- Move from lazy NMI handling to sending siblings in NMI early. This makes
  things more robust, since there might be something we could trip over
  before the handler is called that might be patched by the update.
  [ Suggested by Andy Cooper ]

TBD: Handle DR7, temporarily disable until the update is done
   [ Suggested by Andy Lutomirsky ]


Ashok Raj (4):
  x86/microcode/intel: Check against CPU signature before saving
    microcode
  x86/microcode/intel: Allow a late-load only if a min rev is specified
  x86/microcode: Avoid any chance of MCE's during microcode update
  x86/microcode: Place siblings in NMI loop while update in progress

 arch/x86/include/asm/mce.h             |   4 +
 arch/x86/include/asm/microcode_intel.h |   4 +-
 arch/x86/kernel/cpu/mce/core.c         |   9 ++
 arch/x86/kernel/cpu/microcode/core.c   | 202 ++++++++++++++++++++++++-
 arch/x86/kernel/cpu/microcode/intel.c  |  34 ++++-
 5 files changed, 242 insertions(+), 11 deletions(-)

-- 
2.32.0