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Message-ID: <874jycfa66.fsf@stealth>
Date: Tue, 16 Aug 2022 17:03:13 +0100
From: Punit Agrawal <punit.agrawal@...edance.com>
To: "Yuan, Perry" <Perry.Yuan@....com>
Cc: Punit Agrawal <punit.agrawal@...edance.com>,
"rafael.j.wysocki@...el.com" <rafael.j.wysocki@...el.com>,
"Huang, Ray" <Ray.Huang@....com>,
"viresh.kumar@...aro.org" <viresh.kumar@...aro.org>,
"Sharma, Deepak" <Deepak.Sharma@....com>,
"Limonciello, Mario" <Mario.Limonciello@....com>,
"Fontenot, Nathan" <Nathan.Fontenot@....com>,
"Deucher, Alexander" <Alexander.Deucher@....com>,
"Su, Jinzhou (Joe)" <Jinzhou.Su@....com>,
"Huang, Shimmer" <Shimmer.Huang@....com>,
"Du, Xiaojian" <Xiaojian.Du@....com>,
"Meng, Li (Jassmine)" <Li.Meng@....com>,
"linux-pm@...r.kernel.org" <linux-pm@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v5 6/7] cpufreq: amd-pstate: update pstate frequency
transition delay time
Hi Perry,
"Yuan, Perry" <Perry.Yuan@....com> writes:
> [AMD Official Use Only - General]
>
> Hi Punit
>
>> -----Original Message-----
>> From: Punit Agrawal <punit.agrawal@...edance.com>
>> Sent: Monday, August 15, 2022 11:06 PM
>> To: Yuan, Perry <Perry.Yuan@....com>
>> Cc: rafael.j.wysocki@...el.com; Huang, Ray <Ray.Huang@....com>;
>> viresh.kumar@...aro.org; Sharma, Deepak <Deepak.Sharma@....com>;
>> Limonciello, Mario <Mario.Limonciello@....com>; Fontenot, Nathan
>> <Nathan.Fontenot@....com>; Deucher, Alexander
>> <Alexander.Deucher@....com>; Su, Jinzhou (Joe) <Jinzhou.Su@....com>;
>> Huang, Shimmer <Shimmer.Huang@....com>; Du, Xiaojian
>> <Xiaojian.Du@....com>; Meng, Li (Jassmine) <Li.Meng@....com>; linux-
>> pm@...r.kernel.org; linux-kernel@...r.kernel.org
>> Subject: Re: [PATCH v5 6/7] cpufreq: amd-pstate: update pstate frequency
>> transition delay time
>>
>> [CAUTION: External Email]
>>
>> Perry Yuan <Perry.Yuan@....com> writes:
>>
>> > Change the default transition latency to be 20ms that is more
>> > reasonable transition delay for AMD processors in non-EPP driver mode.
>> >
>> > Update transition delay time to 1ms, in the AMD CPU autonomous mode
>> > and non-autonomous mode, CPPC firmware will decide frequency at 1ms
>> > timescale based on the workload utilization.
>> >
>> > Acked-by: Viresh Kumar <viresh.kumar@...aro.org>
>> > Signed-off-by: Perry Yuan <Perry.Yuan@....com>
>> > ---
>> > drivers/cpufreq/amd-pstate.c | 4 ++--
>> > 1 file changed, 2 insertions(+), 2 deletions(-)
>> >
>> > diff --git a/drivers/cpufreq/amd-pstate.c
>> > b/drivers/cpufreq/amd-pstate.c index e40177d14310..9cb051d61422 100644
>> > --- a/drivers/cpufreq/amd-pstate.c
>> > +++ b/drivers/cpufreq/amd-pstate.c
>> > @@ -41,8 +41,8 @@
>> > #include <asm/msr.h>
>> > #include "amd-pstate-trace.h"
>> >
>> > -#define AMD_PSTATE_TRANSITION_LATENCY 0x20000
>> > -#define AMD_PSTATE_TRANSITION_DELAY 500
>> > +#define AMD_PSTATE_TRANSITION_LATENCY 20000
>> > +#define AMD_PSTATE_TRANSITION_DELAY 1000
>>
>> How were these values derived? If from documentation, it'll be good to add a
>> link to the relevant documentation. And if they were derived from testing,
>> please mention this in the commit log (along with some details of the tests used
>> to determine the value).
>
> The values are calculated from the CPU PM firmware and hardware design.
> There are some latency and delay values defined in the PM firmware, I have no documents about the detail for now.
In that case, please mention that the values are calculated from
firmware / hardware design in the commit log (and include a reference to
the firmware sources if available).
Thanks!
[...]
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