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Message-ID: <CALPaoCjJyYW68Vn1CNbf0Asggyu1AY68DbqcoK5n5FcXqeybJA@mail.gmail.com>
Date: Tue, 16 Aug 2022 19:00:29 +0200
From: Peter Newman <peternewman@...gle.com>
To: Mark Rutland <mark.rutland@....com>
Cc: linux-kernel@...r.kernel.org, peterz@...radead.org,
will@...nel.org, Stephane Eranian <eranian@...gle.com>
Subject: Re: [PATCH v3] perf/arm: adjust hwevents mappings on boot
On Tue, Aug 16, 2022 at 4:18 PM Mark Rutland <mark.rutland@....com> wrote:
> On big.LITTLE systems this is array is shared by multiple PMUs, so this cannot
> be altered based on a single PMU.
>
> Rather than applying a fixup, could we special-case this at mapping time?
>
> Does the following work for you?
>
> Thanks
> Mark.
>
> ---->8----
> From 6cf78ec72194296e8d0c87572b81f2b02a097918 Mon Sep 17 00:00:00 2001
> From: Mark Rutland <mark.rutland@....com>
> Date: Tue, 16 Aug 2022 15:16:23 +0100
> Subject: [PATCH] arm64: pmuv3: dynamically map
> PERF_COUNT_HW_BRANCH_INSTRUCTIONS
>
> Signed-off-by: Mark Rutland <mark.rutland@....com>
Reviewed-by: Peter Newman <peternewman@...gle.com>
Tested-by: Peter Newman <peternewman@...gle.com>
> ---
> arch/arm64/kernel/perf_event.c | 27 +++++++++++++++++++++++----
> 1 file changed, 23 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
> index cb69ff1e61380..0435adee5cab8 100644
> --- a/arch/arm64/kernel/perf_event.c
> +++ b/arch/arm64/kernel/perf_event.c
> @@ -45,7 +45,6 @@ static const unsigned armv8_pmuv3_perf_map[PERF_COUNT_HW_MAX] = {
> [PERF_COUNT_HW_INSTRUCTIONS] = ARMV8_PMUV3_PERFCTR_INST_RETIRED,
> [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
> [PERF_COUNT_HW_CACHE_MISSES] = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
> - [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED,
> [PERF_COUNT_HW_BRANCH_MISSES] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
> [PERF_COUNT_HW_BUS_CYCLES] = ARMV8_PMUV3_PERFCTR_BUS_CYCLES,
> [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV8_PMUV3_PERFCTR_STALL_FRONTEND,
> @@ -1050,6 +1049,28 @@ static void armv8pmu_reset(void *info)
> armv8pmu_pmcr_write(pmcr);
> }
>
> +static int __armv8_pmuv3_map_event_id(struct arm_pmu *armpmu,
> + struct perf_event *event)
> +{
> + if (event->attr.type == PERF_TYPE_HARDWARE &&
> + event->attr.config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) {
> +
> + if (test_bit(ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED,
> + armpmu->pmceid_bitmap))
> + return ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED;
> +
> + if (test_bit(ARMV8_PMUV3_PERFCTR_BR_RETIRED,
> + armpmu->pmceid_bitmap))
> + return ARMV8_PMUV3_PERFCTR_BR_RETIRED;
> +
> + return HW_OP_UNSUPPORTED;
> + }
> +
> + return armpmu_map_event(event, &armv8_pmuv3_perf_map,
> + &armv8_pmuv3_perf_cache_map,
> + ARMV8_PMU_EVTYPE_EVENT);
> +}
> +
> static int __armv8_pmuv3_map_event(struct perf_event *event,
> const unsigned (*extra_event_map)
> [PERF_COUNT_HW_MAX],
> @@ -1061,9 +1082,7 @@ static int __armv8_pmuv3_map_event(struct perf_event *event,
> int hw_event_id;
> struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
>
> - hw_event_id = armpmu_map_event(event, &armv8_pmuv3_perf_map,
> - &armv8_pmuv3_perf_cache_map,
> - ARMV8_PMU_EVTYPE_EVENT);
> + hw_event_id = __armv8_pmuv3_map_event_id(armpmu, event);
>
> if (armv8pmu_event_is_64bit(event))
> event->hw.flags |= ARMPMU_EVT_64BIT;
> --
> 2.30.2
>
Hi Mark,
I can confirm that your patch fixes the issue we saw.
Thank you for coming back with this quickly, it looks like a better
solution to me.
Which branch were you going to apply it to?
Thanks!
-Peter
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