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Message-Id: <166059535262.2709508.15329793193826864091.b4-ty@microchip.com>
Date: Mon, 15 Aug 2022 21:29:37 +0100
From: Conor Dooley <mail@...chuod.ie>
To: conor.dooley@...rochip.com, daire.mcnamara@...rochip.com
Cc: robh+dt@...nel.org, krzysztof.kozlowski+dt@...aro.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-spi@...r.kernel.org, broonie@...nel.org,
nagasuresh.relli@...rochip.com,
valentina.fernandezalanis@...rochip.com,
linux-riscv@...ts.infradead.org
Subject: Re: [PATCH] riscv: dts: microchip: add qspi compatible fallback
From: Conor Dooley <conor.dooley@...rochip.com>
On Wed, 10 Aug 2022 09:59:15 +0100, Conor Dooley wrote:
> The "hard" QSPI peripheral on PolarFire SoC is derived from version 2
> of the FPGA IP core. The original binding had no fallback etc, so this
> device tree is valid as is. There was also no functional driver for the
> QSPI IP, so no device with a devicetree from a previous mainline
> release will regress.
>
>
> [...]
Applied to dt-for-next, thanks!
[1/1] riscv: dts: microchip: add qspi compatible fallback
https://git.kernel.org/conor/c/7eac0081a8e9
Thanks,
Conor.
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