linux-kernel - Re: [PATCH v2 3/9] dt-bindings: clock: Add bindings for Exynos850 CMU

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Message-ID: <bd60a27e-1a47-1f8f-4664-9310aff79344@gmail.com>
Date:   Thu, 18 Aug 2022 04:34:16 +0900
From:   Chanwoo Choi <cwchoi00@...il.com>
To:     Sam Protsenko <semen.protsenko@...aro.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
        Rob Herring <robh+dt@...nel.org>,
        Sylwester Nawrocki <s.nawrocki@...sung.com>,
        Chanwoo Choi <cw00.choi@...sung.com>
Cc:     Alim Akhtar <alim.akhtar@...sung.com>,
        Chanho Park <chanho61.park@...sung.com>,
        David Virag <virag.david003@...il.com>,
        Marek Szyprowski <m.szyprowski@...sung.com>,
        Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...nel.org>,
        Sumit Semwal <sumit.semwal@...aro.org>,
        Tomasz Figa <tomasz.figa@...il.com>,
        devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-samsung-soc@...r.kernel.org
Subject: Re: [PATCH v2 3/9] dt-bindings: clock: Add bindings for Exynos850
 CMU_MFCMSCL

On 22. 8. 9. 20:33, Sam Protsenko wrote:
> CMU_MFCMSCL generates MFC, M2M, MCSC and JPEG clocks for BLK_MFCMSCL.
> Add clock indices and binding documentation for CMU_MFCMSCL.
> 
> Signed-off-by: Sam Protsenko <semen.protsenko@...aro.org>
> ---
> Changes in v2:
>   - (none)
> 
>  .../clock/samsung,exynos850-clock.yaml        | 25 +++++++++++++++
>  include/dt-bindings/clock/exynos850.h         | 32 ++++++++++++++++++-
>  2 files changed, 56 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml
> index 7f2e0b1c764c..141cf173f87d 100644
> --- a/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml
> +++ b/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml
> @@ -39,6 +39,7 @@ properties:
>        - samsung,exynos850-cmu-dpu
>        - samsung,exynos850-cmu-hsi
>        - samsung,exynos850-cmu-is
> +      - samsung,exynos850-cmu-mfcmscl
>        - samsung,exynos850-cmu-peri
>  
>    clocks:
> @@ -216,6 +217,30 @@ allOf:
>              - const: dout_is_vra
>              - const: dout_is_gdc
>  
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: samsung,exynos850-cmu-mfcmscl
> +
> +    then:
> +      properties:
> +        clocks:
> +          items:
> +            - description: External reference clock (26 MHz)
> +            - description: Multi-Format Codec clock (from CMU_TOP)
> +            - description: Memory to Memory Scaler clock (from CMU_TOP)
> +            - description: Multi-Channel Scaler clock (from CMU_TOP)
> +            - description: JPEG codec clock (from CMU_TOP)
> +
> +        clock-names:
> +          items:
> +            - const: oscclk
> +            - const: dout_mfcmscl_mfc
> +            - const: dout_mfcmscl_m2m
> +            - const: dout_mfcmscl_mcsc
> +            - const: dout_mfcmscl_jpeg
> +
>    - if:
>        properties:
>          compatible:
> diff --git a/include/dt-bindings/clock/exynos850.h b/include/dt-bindings/clock/exynos850.h
> index f8bf26f118c1..88d5289883d3 100644
> --- a/include/dt-bindings/clock/exynos850.h
> +++ b/include/dt-bindings/clock/exynos850.h
> @@ -73,7 +73,19 @@
>  #define CLK_DOUT_IS_ITP			61
>  #define CLK_DOUT_IS_VRA			62
>  #define CLK_DOUT_IS_GDC			63
> -#define TOP_NR_CLK			64
> +#define CLK_MOUT_MFCMSCL_MFC		64
> +#define CLK_MOUT_MFCMSCL_M2M		65
> +#define CLK_MOUT_MFCMSCL_MCSC		66
> +#define CLK_MOUT_MFCMSCL_JPEG		67
> +#define CLK_GOUT_MFCMSCL_MFC		68
> +#define CLK_GOUT_MFCMSCL_M2M		69
> +#define CLK_GOUT_MFCMSCL_MCSC		70
> +#define CLK_GOUT_MFCMSCL_JPEG		71
> +#define CLK_DOUT_MFCMSCL_MFC		72
> +#define CLK_DOUT_MFCMSCL_M2M		73
> +#define CLK_DOUT_MFCMSCL_MCSC		74
> +#define CLK_DOUT_MFCMSCL_JPEG		75
> +#define TOP_NR_CLK			76
>  
>  /* CMU_APM */
>  #define CLK_RCO_I3C_PMIC		1
> @@ -225,6 +237,24 @@
>  #define CLK_GOUT_IS_SYSREG_PCLK		23
>  #define IS_NR_CLK			24
>  
> +/* CMU_MFCMSCL */
> +#define CLK_MOUT_MFCMSCL_MFC_USER		1
> +#define CLK_MOUT_MFCMSCL_M2M_USER		2
> +#define CLK_MOUT_MFCMSCL_MCSC_USER		3
> +#define CLK_MOUT_MFCMSCL_JPEG_USER		4
> +#define CLK_DOUT_MFCMSCL_BUSP			5
> +#define CLK_GOUT_MFCMSCL_CMU_MFCMSCL_PCLK	6
> +#define CLK_GOUT_MFCMSCL_TZPC_PCLK		7
> +#define CLK_GOUT_MFCMSCL_JPEG_ACLK		8
> +#define CLK_GOUT_MFCMSCL_M2M_ACLK		9
> +#define CLK_GOUT_MFCMSCL_MCSC_CLK		10
> +#define CLK_GOUT_MFCMSCL_MFC_ACLK		11
> +#define CLK_GOUT_MFCMSCL_PPMU_ACLK		12
> +#define CLK_GOUT_MFCMSCL_PPMU_PCLK		13
> +#define CLK_GOUT_MFCMSCL_SYSMMU_CLK		14
> +#define CLK_GOUT_MFCMSCL_SYSREG_PCLK		15
> +#define MFCMSCL_NR_CLK				16
> +
>  /* CMU_PERI */
>  #define CLK_MOUT_PERI_BUS_USER		1
>  #define CLK_MOUT_PERI_UART_USER		2

Reviewed-by: Chanwoo Choi <cw00.choi@...sung.com>

-- 
Best Regards,
Samsung Electronics
Chanwoo Choi