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Message-Id: <20220817202538.21493-3-leoyang.li@nxp.com>
Date: Wed, 17 Aug 2022 15:25:38 -0500
From: Li Yang <leoyang.li@....com>
To: shawnguo@...nel.org, devicetree@...r.kernel.org
Cc: robh+dt@...nel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org, Xiaowei Bao <xiaowei.bao@....com>,
Li Yang <leoyang.li@....com>,
Hou Zhiqiang <Zhiqiang.Hou@....com>
Subject: [PATCH v4 2/2] arm64: dts: lx2160a: add pcie EP mode nodes
From: Xiaowei Bao <xiaowei.bao@....com>
The LX2160A PCIe EP mode nodes based on controller used on lx2160a rev2.
Signed-off-by: Xiaowei Bao <xiaowei.bao@....com>
Signed-off-by: Li Yang <leoyang.li@....com>
Reviewed-by: Hou Zhiqiang <Zhiqiang.Hou@....com>
---
.../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 60 +++++++++++++++++++
1 file changed, 60 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index a7c549277dcc..97786b454ec7 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -1131,6 +1131,16 @@ pcie1: pcie@...0000 {
status = "disabled";
};
+ pcie_ep1: pcie-ep@...0000 {
+ compatible = "fsl,lx2160ar2-pcie-ep", "fsl,ls-pcie-ep";
+ reg = <0x00 0x03400000 0x0 0x00100000
+ 0x80 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "addr_space";
+ num-ob-windows = <8>;
+ num-ib-windows = <8>;
+ status = "disabled";
+ };
+
pcie2: pcie@...0000 {
compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
@@ -1159,6 +1169,16 @@ pcie2: pcie@...0000 {
status = "disabled";
};
+ pcie_ep2: pcie-ep@...0000 {
+ compatible = "fsl,lx2160ar2-pcie-ep", "fsl,ls-pcie-ep";
+ reg = <0x00 0x03500000 0x0 0x00100000
+ 0x88 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "addr_space";
+ num-ob-windows = <8>;
+ num-ib-windows = <8>;
+ status = "disabled";
+ };
+
pcie3: pcie@...0000 {
compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
@@ -1187,6 +1207,16 @@ pcie3: pcie@...0000 {
status = "disabled";
};
+ pcie_ep3: pcie-ep@...0000 {
+ compatible = "fsl,lx2160ar2-pcie-ep", "fsl,ls-pcie-ep";
+ reg = <0x00 0x03600000 0x0 0x00100000
+ 0x90 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "addr_space";
+ num-ob-windows = <256>;
+ num-ib-windows = <24>;
+ status = "disabled";
+ };
+
pcie4: pcie@...0000 {
compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
@@ -1215,6 +1245,16 @@ pcie4: pcie@...0000 {
status = "disabled";
};
+ pcie_ep4: pcie-ep@...0000 {
+ compatible = "fsl,lx2160ar2-pcie-ep", "fsl,ls-pcie-ep";
+ reg = <0x00 0x03700000 0x0 0x00100000
+ 0x98 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "addr_space";
+ num-ob-windows = <8>;
+ num-ib-windows = <8>;
+ status = "disabled";
+ };
+
pcie5: pcie@...0000 {
compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
reg = <0x00 0x03800000 0x0 0x00100000 /* controller registers */
@@ -1243,6 +1283,16 @@ pcie5: pcie@...0000 {
status = "disabled";
};
+ pcie_ep5: pcie-ep@...0000 {
+ compatible = "fsl,lx2160ar2-pcie-ep", "fsl,ls-pcie-ep";
+ reg = <0x00 0x03800000 0x0 0x00100000
+ 0xa0 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "addr_space";
+ num-ob-windows = <256>;
+ num-ib-windows = <24>;
+ status = "disabled";
+ };
+
pcie6: pcie@...0000 {
compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
reg = <0x00 0x03900000 0x0 0x00100000 /* controller registers */
@@ -1271,6 +1321,16 @@ pcie6: pcie@...0000 {
status = "disabled";
};
+ pcie_ep6: pcie-ep@...0000 {
+ compatible = "fsl,lx2160ar2-pcie-ep", "fsl,ls-pcie-ep";
+ reg = <0x00 0x03900000 0x0 0x00100000
+ 0xa8 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "addr_space";
+ num-ob-windows = <8>;
+ num-ib-windows = <8>;
+ status = "disabled";
+ };
+
smmu: iommu@...0000 {
compatible = "arm,mmu-500";
reg = <0 0x5000000 0 0x800000>;
--
2.37.1
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