linux-kernel - [PATCH v3] PCI/PM: Switch D3Hot delay to also use usleep

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [thread-next>] [day] [month] [year] [list]

Message-Id: <20220817230821.47048-1-willmcvicker@google.com>
Date:   Wed, 17 Aug 2022 23:08:21 +0000
From:   Will McVicker <willmcvicker@...gle.com>
To:     Bjorn Helgaas <bhelgaas@...gle.com>
Cc:     kernel-team@...roid.com, Sajid Dalvi <sdalvi@...gle.com>,
        Matthias Kaehlcke <mka@...omium.org>,
        Will McVicker <willmcvicker@...gle.com>,
        linux-pci@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: [PATCH v3] PCI/PM: Switch D3Hot delay to also use usleep_range

From: Sajid Dalvi <sdalvi@...gle.com>

Since the PCI spec requires a 10ms D3Hot delay (defined by
PCI_PM_D3HOT_WAIT) and a few of the PCI quirks update the D3Hot delay up
to 120ms, let's add support for both usleep_range and msleep based on
the delay time to improve the delay accuracy.

This patch is based off of a commit from Sajid Dalvi <sdalvi@...gle.com>
in the Pixel 6 kernel tree [1]. Testing on a Pixel 6, found that the
10ms delay for the Exynos PCIe device was on average delaying for 19ms
when the spec requires 10ms. Switching from msleep to uslseep_range
therefore decreases the resume time on a Pixel 6 on average by 9ms.

[1] https://android.googlesource.com/kernel/gs/+/18a8cad68d8e6d50f339a716a18295e6d987cee3

Signed-off-by: Sajid Dalvi <sdalvi@...gle.com>
Signed-off-by: Will McVicker <willmcvicker@...gle.com>
---
 drivers/pci/pci.c | 16 +++++++++++-----
 1 file changed, 11 insertions(+), 5 deletions(-)

v3:
 * Use DIV_ROUND_CLOSEST instead of bit manipulation.
 * Minor refactor to use max() where relavant.

v2:
 * Update to use 20-25% upper bound
 * Update to use usleep_range() for <=20ms, else use msleep()

diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 95bc329e74c0..cfa8386314f2 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -66,13 +66,19 @@ struct pci_pme_device {
 
 static void pci_dev_d3_sleep(struct pci_dev *dev)
 {
-	unsigned int delay = dev->d3hot_delay;
+	unsigned int delay_ms = max(dev->d3hot_delay, pci_pm_d3hot_delay);
 
-	if (delay < pci_pm_d3hot_delay)
-		delay = pci_pm_d3hot_delay;
+	if (delay_ms) {
+		if (delay_ms <= 20) {
+			/* Use a 20% upper bound with 1ms minimum */
+			unsigned int upper = max(DIV_ROUND_CLOSEST(delay_ms, 5), 1U);
 
-	if (delay)
-		msleep(delay);
+			usleep_range(delay_ms * USEC_PER_MSEC,
+				     (delay_ms + upper) * USEC_PER_MSEC);
+		} else {
+			msleep(delay_ms);
+		}
+	}
 }
 
 bool pci_reset_supported(struct pci_dev *dev)

base-commit: 274a2eebf80c60246f9edd6ef8e9a095ad121264
-- 
2.37.1.595.g718a3a8f04-goog