linux-kernel - [PATCH v9,5/7] arm64: dts: mt8195: Add efuse node to mt8195

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Wed, 17 Aug 2022 10:07:55 +0200
From:   bchihi@...libre.com
To:     rafael@...nel.org, rui.zhang@...el.com, daniel.lezcano@...aro.org,
        amitk@...nel.org
Cc:     linux-pm@...r.kernel.org, linux-kernel@...r.kernel.org,
        khilman@...libre.com, mka@...omium.org, robh+dt@...nel.org,
        krzk+dt@...nel.org, matthias.bgg@...il.com, p.zabel@...gutronix.de,
        devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-mediatek@...ts.infradead.org, james.lo@...iatek.com,
        fan.chen@...iatek.com, louis.yu@...iatek.com,
        rex-bc.chen@...iatek.com, abailon@...libre.com
Subject: [PATCH v9,5/7] arm64: dts: mt8195: Add efuse node to mt8195

From: Alexandre Bailon <abailon@...libre.com>

Add efuse node.
This will be required by the thermal driver to get the calibration data.

Signed-off-by: Alexandre Bailon <abailon@...libre.com>
Co-developed-by: Balsam CHIHI <bchihi@...libre.com>
Signed-off-by: Balsam CHIHI <bchihi@...libre.com>
---
 arch/arm64/boot/dts/mediatek/mt8195.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 066c14989708..95967a0196d8 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -733,6 +733,18 @@ u2_intr_p3: usb2-intr-p3@189,2 {
 				reg = <0x189 0x2>;
 				bits = <7 5>;
 			};
+
+			lvts_efuse_data1: lvts1-calib@1bc {
+				reg = <0x1bc 0x14>;
+			};
+
+			lvts_efuse_data2: lvts2-calib@1d0 {
+				reg = <0x1d0 0x38>;
+			};
+
+			svs_calibration: calib@580 {
+				reg = <0x580 0x64>;
+			};
 		};
 
 		u3phy2: t-phy@...40000 {
-- 
2.34.1