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Date: Thu, 18 Aug 2022 21:19:49 +0100 From: Conor Dooley <mail@...chuod.ie> To: Heinrich Schuchardt <heinrich.schuchardt@...onical.com>, Rob Herring <robh+dt@...nel.org> Cc: Conor Dooley <conor.dooley@...rochip.com>, linux-riscv@...ts.infradead.org, stable@...r.kernel.org, Palmer Dabbelt <palmer@...belt.com>, Krzysztof Kozlowski <krzk@...nel.org>, Albert Ou <aou@...s.berkeley.edu>, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, Paul Walmsley <paul.walmsley@...ive.com>, Atish Patra <atishp@...shpatra.org>, Emil Renner Berthing <emil.renner.berthing@...onical.com>, Geert Uytterhoeven <geert@...ux-m68k.org> Subject: Re: [PATCH 1/1] riscv: dts: microchip: correct L2 cache interrupts From: Conor Dooley <conor.dooley@...rochip.com> On Wed, 17 Aug 2022 15:25:21 +0200, Heinrich Schuchardt wrote: > The "PolarFire SoC MSS Technical Reference Manual" documents the > following PLIC interrupts: > > 1 - L2 Cache Controller Signals when a metadata correction event occurs > 2 - L2 Cache Controller Signals when an uncorrectable metadata event occurs > 3 - L2 Cache Controller Signals when a data correction event occurs > 4 - L2 Cache Controller Signals when an uncorrectable data event occurs > > [...] Added the impact of the bug & applied to dt-fixes, thanks! [1/1] riscv: dts: microchip: correct L2 cache interrupts https://git.kernel.org/conor/c/34fc9cc3aebe8b9 Thanks, Conor.
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