Message-ID: <994ad6ea-5d3f-b3d1-e0e5-883530ebaf2a@microchip.com>
Date:   Thu, 18 Aug 2022 21:10:54 +0000
From:   <Conor.Dooley@...rochip.com>
To:     <palmer@...belt.com>
CC:     <sudeep.holla@....com>, <catalin.marinas@....com>,
        <will@...nel.org>, <linux-riscv@...ts.infradead.org>,
        <linux-kernel@...r.kernel.org>, <Conor.Dooley@...rochip.com>,
        <linux-arm-kernel@...ts.infradead.org>, <atishp@...shpatra.org>,
        <Brice.Goglin@...ia.fr>, <gregkh@...uxfoundation.org>
Subject: Re: [GIT PULL] Fix RISC-V's arch-topology reporting



On 18/08/2022 22:03, Palmer Dabbelt wrote:
> On Mon, 15 Aug 2022 15:14:55 PDT (-0700), Conor.Dooley@...rochip.com wrote:
>> Hey Will/Palmer/Sudeep,
>>
>> Catalin suggested [0] dropping the CC: stable for the arm64 patch and
>> instead making it a specific prereq of the RISC-V patch & making a PR,
>> so here we are.. I was still up when -rc1 came out so pushed it last
>> night to get the test coverage, but LKP seems to not have reported a
>> build success since early on the 13th so not holding my horses! I built
>> it again for both ARMs and RISC-V myself.
>>
>> I tagged it tonight, so it's on conor/linux.git as riscv-topo-on-6.0-rc1
>> with the prereq specified.
>>
>> Not sure if you want to merge this too Sudeep or if that's up to Greg?
> 
> It's a little bit vague what you're asking for here, so I'm just
> going to kind of guessing here but this on riscv/for-next.  I'm not
> sure if you were looking for me to just merge the arch/riscv bits or
> if this should be on fixes (just looking at the patch makes it look
> like it should be), but I don't want to send up some arm64 code to
> fixes without it being pretty explicit that I should do so

Ahh sorry, I completely forgot to mention that Will said "for 5.21" in
his response to my original patchset. for-next sounds fine to me - all
in-tree devicetrees had the optional properties added to them that solve
the issue - and they were AUTOSEL'ed too from what I can see.

Thanks & sorry!
Conor.

> 
> Acked-by: Palmer Dabbelt <palmer@...osinc.com> # arch/riscv bits, for 6.0-rc
> 
> in case someone else wants to send it up before I get back to this,
> I'm fine either way.
> 
> Thanks!
> 
>>
>> Thanks,
>> Conor.
>>
>> 0 - https://lore.kernel.org/linux-riscv/Ytac7G1zlq6WW4jt@arm.com/
>>
>> The following changes since commit 568035b01cfb107af8d2e4bd2fb9aea22cf5b868:
>>
>>   Linux 6.0-rc1 (2022-08-14 15:50:18 -0700)
>>
>> are available in the Git repository at:
>>
>>   https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ tags/riscv-topo-on-6.0-rc1
>>
>> for you to fetch changes up to fbd92809997a391f28075f1c8b5ee314c225557c:
>>
>>   riscv: topology: fix default topology reporting (2022-08-15 22:07:34 +0100)
>>
>> ----------------------------------------------------------------
>> Fix RISC-V's topology reporting
>>
>> The goal here is the fix the incorrectly reported arch topology on
>> RISC-V which seems to have been broken since it was added.
>> cpu, package and thread IDs are all currently reported as -1, so tools
>> like lstopo think systems have multiple threads on the same core when
>> this is not true:
>> https://github.com/open-mpi/hwloc/issues/536
>>
>> arm64's topology code basically applies to RISC-V too, so it has been
>> made generic along with the removal of MPIDR related code, which
>> appears to be redudant code since '3102bc0e6ac7 ("arm64: topology: Stop
>> using MPIDR for topology information")' replaced the code that actually
>> interacted with MPIDR with default values.
>>
>> ----------------------------------------------------------------
>> Conor Dooley (2):
>>       arm64: topology: move store_cpu_topology() to shared code
>>       riscv: topology: fix default topology reporting
>>
>>  arch/arm64/kernel/topology.c | 40 ----------------------------------------
>>  arch/riscv/Kconfig           |  2 +-
>>  arch/riscv/kernel/smpboot.c  |  3 ++-
>>  drivers/base/arch_topology.c | 19 +++++++++++++++++++
>>  4 files changed, 22 insertions(+), 42 deletions(-)
> 
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@...ts.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv

Powered by blists - more mailing lists